Preliminary Datasheet EZ-PD CCG6DF, CCG6SF (Cypress) - 44

PRELIMINARY EZ-PD CCG6DF, CCG6SF Figure 24. 96-ball BGA (6 × 6 × 0.5 mm), 6.0 × 6.0 x 1.0 mm Package Outline
E1 2X 0.10 C (datum B) E B A1 CORNER A 11 10 9 8 7 6 5 4 3 2 1 7 A A1 CORNER B 6 C SD D E F D1 D G (datum A) H J K L eD 0.10 C 2X 6 eE SE TOP VIEW BOTTOM VIEW DETAIL A 0.10 C A A1 C 0.08 C 96XØb 5 Ø0.15 M C A B SIDE VIEW Ø0.05 M C DETAIL A NOTES: DIMENSIONS 1. ALL DIMENSIONS ARE IN MILLIMETERS. SYMBOL 2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. MIN. NOM. MAX. A 3. "e" REPRESENTS THE SOLDER BALL GRID PITCH. - - 1.00 A1 0.16 - - 4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. D 6.00 BSC N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX E 6.00 BSC SIZE MD X ME. D1 5.00 BSC 5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A E1 5.00 BSC PLANE PARALLEL TO DATUM C. MD 11 6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND ME 11 DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW N 96 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW b 0.25 0.30 0.35 "SD" OR "SE" = 0. eD 0.50 BSC WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW eE 0.50 BSC "SD" = eD/2 AND "SE" = eE/2. SD 0.00 7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK SE 0.00 METALIZED MARK, INDENTATION OR OTHER MEANS. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER BALLS. 9. JEDEC SPECIFICATION NO. REF. : MO-225. 002-10631 *B Document Number: 002-27161 Rev. *E Page 44 of 50 Document Outline EZ-PD CCG6DF, CCG6SF, USB Type-C Port Controller General Description Applications Features USB-PD Type-C Mux Integrated Provider VBUS Load Switch LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Logic Block Diagram CCG6DF/CCG6SF Functional Diagram Contents Functional Overview MCU Subsystem CPU Flash, SROM, and RAM USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC SBU Pass-Through Switch and USB HS Mux Provider Load Switch Undervoltage and Overvoltage Protection on VBUS High-side Current Sense Amplifier for VBUS VBUS Reverse Current Protection VBUS Short Circuit Protection VBUS Discharge VBUS Regulator Gate Driver for VBUS NFET VBUS Tolerant SBU and CC Lines Serial Communication Block (SCB) Timer, Counter, Pulse-Width Modulator (TCPWM) True Random Number Generator (TRNG) GPIO Interface System Resources Watchdog Timer (WDT) Clock System IMO Clock Source ILO Clock Source Power Pinouts Application Diagrams CCG6DF, CCG6SF Layout Design Guidelines for BGA Package Usage of Via Size of 8-mil drill/16-mil diameter and 10-mil drill/16-mil diameter Layer Stack-up Top Layer Fan Out Via Count for GND Pads Via Count for Provider Pads High-Speed (DP_SYS, DM_SYS) USB Connections CC Connections CC lines for CCG6DF/CCG6SF devices carry ~500-mA current. In the top layer, two CC pads are shorted using 0.2mm trace width and connected to other layers through one via. The capacitors are placed on bottom layer and are routed to the Type-C Connecto... Rsense and Capacitor Connections for Provider VBUS The differential signal from Rsense should be length matched. The capacitor for Provider VBUS should be as close as possible to the Rsense and connected using copper shape. Figure 19 and Figure 20 show routing for Rsense. Trace Width Details for Critical Signals VDDIO, VCCD, VSYS, and VDDD Connections Figure 21 and Figure 22 show how the VDDIO, VDDD, VSYS, and VCCD signals get routed amongst the top and bottom layers. Capacitor Connections for CC Lines and Bypass Capacitors for VDDIO, VDDD, VCCD, and VSYS Pins Figure 23 shows how the relevant capacitors can be placed for via sizes of 8-mil drill, 16-mil diameter or 10-mil drill, 16-mil diameter. Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter VSYS Switch CSA VBUS UV/OV Provider Side RCP SBU Switch DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure References and Links to Applications Collateral Knowledge Base Articles Application Notes Reference Designs Kits Datasheets Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support