Datasheet ACS37612 (Allegro) - 21
| Manufacturer | Allegro |
| Description | Coreless, High Precision, Hall-Effect Current Sensor IC with Common-Mode Field Rejection and High Bandwidth (240 kHz) |
| Pages / Page | 22 / 21 — Coreless, High Precision, Hall-Effect Current Sensor IC. ACS37612 |
| File Format / Size | PDF / 2.3 Mb |
| Document Language | English |
Coreless, High Precision, Hall-Effect Current Sensor IC. ACS37612
Model Line for this Datasheet
Text Version of Document
Coreless, High Precision, Hall-Effect Current Sensor IC ACS37612 with Common-Mode Field Rejection and High Bandwidth (240 kHz) PACKAGE OUTLINE DRAWING For Reference Only – Not for Tooling Use
(Reference MO-153 AA) NOT TO SCALE Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 3.00 ±0.10 D 0.45 8º 0.65 0º 8 8 0.20 1.70 0.09 E E2 E E1 6.40 BSC 4.40 ±0.10 1.87 6.10 3.15 E 0.60+0.15 –0.10 A E 1.27 1.00 REF 1 2 1.70 0.25 BSC 1 2 E SEATING PLANE B PCB Layout Reference View Branded Face GAUGE PLANE C 8× 1.10 MAX 0.10 C SEATING PLANE 0.30 XXX 0.19 0.15 0.05 Date Code 0.65 BSC A Terminal #1 mark area B Reference land pattern layout (reference IPC7351 SOP65P640X110-8M); all pads a minimum of 0.20 mm from all adjacent pads; C Standard Branding Reference View adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, Line 1: Maximum 3 characters thermal vias can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Line 2: Maximum 5 characters C Branding scale and appearance at supplier discretion Line 1: Part Number Line 2: Logo A, 4-digit Date Code D Active Area Depth 0.36 mm REF E Hall elements (E1, E2); not to scale.
Figure 24: Package LU, 8-Pin TSSOP Package
21 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com
(Reference MO-153 AA) NOT TO SCALE Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 3.00 ±0.10 D 0.45 8º 0.65 0º 8 8 0.20 1.70 0.09 E E2 E E1 6.40 BSC 4.40 ±0.10 1.87 6.10 3.15 E 0.60+0.15 –0.10 A E 1.27 1.00 REF 1 2 1.70 0.25 BSC 1 2 E SEATING PLANE B PCB Layout Reference View Branded Face GAUGE PLANE C 8× 1.10 MAX 0.10 C SEATING PLANE 0.30 XXX 0.19 0.15 0.05 Date Code 0.65 BSC A Terminal #1 mark area B Reference land pattern layout (reference IPC7351 SOP65P640X110-8M); all pads a minimum of 0.20 mm from all adjacent pads; C Standard Branding Reference View adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, Line 1: Maximum 3 characters thermal vias can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Line 2: Maximum 5 characters C Branding scale and appearance at supplier discretion Line 1: Part Number Line 2: Logo A, 4-digit Date Code D Active Area Depth 0.36 mm REF E Hall elements (E1, E2); not to scale.
Figure 24: Package LU, 8-Pin TSSOP Package
21 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com
