Datasheet LTC6994-1, LTC6994-2 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | TimerBlox: Delay Block/Debouncer |
| Pages / Page | 28 / 10 — PIN FUNCTIONS (DCB/S6). V+ (Pin 1/Pin 5):. DIV (Pin 2/Pin 4):. IN (Pin … |
| Revision | C |
| File Format / Size | PDF / 766 Kb |
| Document Language | English |
PIN FUNCTIONS (DCB/S6). V+ (Pin 1/Pin 5):. DIV (Pin 2/Pin 4):. IN (Pin 4/Pin 1):. SET (Pin 3/Pin 3):. GND (Pin 5/Pin 2):
Model Line for this Datasheet
- LTC6994CDCB-1#TRMPBF LTC6994CDCB-1#TRPBF LTC6994CDCB-2#TRMPBF LTC6994CDCB-2#TRPBF LTC6994CS6-1#TRMPBF LTC6994CS6-1#TRPBF LTC6994CS6-2#TRMPBF LTC6994CS6-2#TRPBF LTC6994HDCB-1#TRMPBF LTC6994HDCB-1#TRPBF LTC6994HDCB-2#TRMPBF LTC6994HDCB-2#TRPBF LTC6994HS6-1#TRMPBF LTC6994HS6-1#TRPBF LTC6994HS6-1#WTRMPBF LTC6994HS6-1#WTRPBF LTC6994HS6-2#TRMPBF LTC6994HS6-2#TRPBF LTC6994HS6-2#WTRMPBF LTC6994HS6-2#WTRPBF LTC6994IDCB-1#TRMPBF LTC6994IDCB-1#TRPBF LTC6994IDCB-2#TRMPBF LTC6994IDCB-2#TRPBF LTC6994IS6-1#TRMPBF LTC6994IS6-1#TRPBF LTC6994IS6-1#WTRMPBF LTC6994IS6-1#WTRPBF LTC6994IS6-2#TRMPBF LTC6994IS6-2#TRPBF LTC6994IS6-2#WTRMPBF LTC6994IS6-2#WTRPBF LTC6994MPS6-1#TRMPBF LTC6994MPS6-1#TRPBF LTC6994MPS6-2#TRMPBF LTC6994MPS6-2#TRPBF
Text Version of Document
LTC6994-1/LTC6994-2
PIN FUNCTIONS (DCB/S6) V+ (Pin 1/Pin 5):
Supply Voltage (2.25V to 5.5V). This sup- A resistor connected between SET and GND is the most ply should be kept free from noise and ripple. It should be accurate way to set the delay. For best performance, use bypassed directly to the GND pin with a 0.1µF capacitor. a precision metal or thin film resistor of 0.5% or better
DIV (Pin 2/Pin 4):
Programmable Divider and Polarity tolerance and 50ppm/°C or better temperature coefficient. Input. The DIV pin voltage (V For lower accuracy applications an inexpensive 1% thick DIV) is internally converted into a 4-bit result (DIVCODE). V film resistor may be used. DIV may be generated by a resistor divider between V+ and GND. Use 1% resistors Limit the capacitance on the SET pin to less than 10pF to ensure an accurate result. The DIV pin and resistors to minimize jitter and ensure stability. Capacitance less should be shielded from the OUT pin or any other traces than 100pF maintains the stability of the feedback circuit that have fast edges. Limit the capacitance on the DIV pin regulating the VSET voltage. to less than 100pF so that VDIV settles quickly. The MSB of DIVCODE (POL) selects the delay functionality. For the
IN (Pin 4/Pin 1):
Logic Input. Depending on the version and LTC6994-1, POL = 0 will delay the rising transition and POL bit setting, rising or falling edges on IN will propagate POL = 1 will delay the falling transition. For the LTC6994- to OUT after a programmable delay. The LTC6994-1 will 2, both transitions are delayed so POL = 1 can be used delay only the rising or falling edge. The LTC6994-2 will to invert the output. delay both edges.
SET (Pin 3/Pin 3):
Delay Setting Input. The voltage on the
GND (Pin 5/Pin 2):
Ground. Tie to a low inductance ground SET pin (V plane for best performance. SET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) programs the
OUT (Pin 6/Pin 6):
Output. The OUT pin swings from master oscillator frequency. The ISET current range is GND to V+ with an output resistance of approximately 1.25µA to 20µA. The delayed output transition will be not 30Ω. When driving an LED or other low impedance load occur if ISET drops below approximately 500nA. Once ISET a series output resistor should be used to limit source/ increases above 500nA the delayed edge will transition. sink current to 20mA. V+ IN OUT LTC6994 V+ GND V+ C1 0.1µF R1 SET DIV 699412 PF RSET R2 Rev. C 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS (DCB/S6) V+ (Pin 1/Pin 5):
Supply Voltage (2.25V to 5.5V). This sup- A resistor connected between SET and GND is the most ply should be kept free from noise and ripple. It should be accurate way to set the delay. For best performance, use bypassed directly to the GND pin with a 0.1µF capacitor. a precision metal or thin film resistor of 0.5% or better
DIV (Pin 2/Pin 4):
Programmable Divider and Polarity tolerance and 50ppm/°C or better temperature coefficient. Input. The DIV pin voltage (V For lower accuracy applications an inexpensive 1% thick DIV) is internally converted into a 4-bit result (DIVCODE). V film resistor may be used. DIV may be generated by a resistor divider between V+ and GND. Use 1% resistors Limit the capacitance on the SET pin to less than 10pF to ensure an accurate result. The DIV pin and resistors to minimize jitter and ensure stability. Capacitance less should be shielded from the OUT pin or any other traces than 100pF maintains the stability of the feedback circuit that have fast edges. Limit the capacitance on the DIV pin regulating the VSET voltage. to less than 100pF so that VDIV settles quickly. The MSB of DIVCODE (POL) selects the delay functionality. For the
IN (Pin 4/Pin 1):
Logic Input. Depending on the version and LTC6994-1, POL = 0 will delay the rising transition and POL bit setting, rising or falling edges on IN will propagate POL = 1 will delay the falling transition. For the LTC6994- to OUT after a programmable delay. The LTC6994-1 will 2, both transitions are delayed so POL = 1 can be used delay only the rising or falling edge. The LTC6994-2 will to invert the output. delay both edges.
SET (Pin 3/Pin 3):
Delay Setting Input. The voltage on the
GND (Pin 5/Pin 2):
Ground. Tie to a low inductance ground SET pin (V plane for best performance. SET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) programs the
OUT (Pin 6/Pin 6):
Output. The OUT pin swings from master oscillator frequency. The ISET current range is GND to V+ with an output resistance of approximately 1.25µA to 20µA. The delayed output transition will be not 30Ω. When driving an LED or other low impedance load occur if ISET drops below approximately 500nA. Once ISET a series output resistor should be used to limit source/ increases above 500nA the delayed edge will transition. sink current to 20mA. V+ IN OUT LTC6994 V+ GND V+ C1 0.1µF R1 SET DIV 699412 PF RSET R2 Rev. C 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
