Datasheet IX4351NE (IXYS) - 9
| Manufacturer | IXYS |
| Description | 9A Low Side SiC MOSFET & IGBT Driver |
| Pages / Page | 12 / 9 — IX4351NE. Functional Description. Figure 1. IX4351NE Typical Application … |
| File Format / Size | PDF / 334 Kb |
| Document Language | English |
IX4351NE. Functional Description. Figure 1. IX4351NE Typical Application Circuit. 4.1 Logic Input (IN)
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IX4351NE
NTEGRATED CIRCUITS DIVISION
4 Functional Description
The IX4351NE is designed to provide the gate drive for high power SiC MOSFETs and IGBTs.
Figure 1. IX4351NE Typical Application Circuit
VDD R D1 DRAIN DESAT DESAT IN 4 6 6.8V CBLANK VDD 2 +22V 3 C Controller DD OUTSRC RH Gate and 1 FAULT Control OUTSNK 5 16 Logic RL VSS GATE 15 10 R OUTSOFT SOFT 14 SOURCE VDD VSS VREG INSOFT 4.6V 13 8 Regulator 2.6V V R1 DD C SET FLY Charge CAP CREG 9 Pump 12 Control RFLY CSS GND R2 11 COM 7 VSS
4.1 Logic Input (IN) 4.2 Gate Drive Outputs (OUTSRC and OUTSNK)
The logic input IN controls the state of the high current The IX4351NE power outputs are rated for 9A peak source driver output (OUTSRC), high current sink current capability. Separate source and sink outputs driver output (OUTSNK), and the lower current sink allow independent adjustment of the discrete SiC driver output (OUTSOFT). The IN input is a MOSFET or IGBT turn-on and turn-off transactions high-speed Schmitt trigger buffer with 0.4V hysteresis. with a single resistor. An internal dead time prevents The IN logic thresholds are TTL and CMOS cross conduction of the source and sink outputs. compatible, and are referenced to COM. When VDD is greater than the V
4.3 Internal 4.6V Regulator (VREG)
DD UVLO rising threshold (VDDUV+), typically 12V, IN controls the state of the gate driver The internal 4.6V regulator provides power for the low outputs according to Table 1: voltage control circuitry. An external 4.7F bypass capacitor (CREG) is required. VREG can source up to 4.1.1 Table 1 10mA, that can be used to set the negative bias
IN V
voltage and power an external logic optocoupler.
DD OUTSRC OUTSNK OUTSOFT
X < VDDUV+ Off Low Low 0 > VDDUV+ Off Low Low 1 > VDDUV+ High Off Off R02
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9 Document Outline Features Applications Description Ordering Information 1 Specifications 1.1 Package Pinout 1.2 Pin Description 1.3 Absolute Maximum Ratings 1.4 Recommended Operating Conditions 1.5 Electrical Characteristics 1.6 Thermal Characteristics 2 Performance Data 3 Performance Data (Cont.) 4 Functional Description 4.1 Logic Input (IN) 4.2 Gate Drive Outputs (OUTSRC and OUTSNK) 4.3 Internal 4.6V Regulator (VREG) 4.4 Negative VSS Charge Pump Regulator 4.5 Desaturation Detection and Protection 4.6 Thermal Shutdown 4.7 FAULT Output 5 Manufacturing Information 5.1 Moisture Sensitivity 5.2 ESD Sensitivity 5.3 Soldering Profile 5.4 Board Wash 5.5 Mechanical Dimensions
IX4351NE
NTEGRATED CIRCUITS DIVISION
4 Functional Description
The IX4351NE is designed to provide the gate drive for high power SiC MOSFETs and IGBTs.
Figure 1. IX4351NE Typical Application Circuit
VDD R D1 DRAIN DESAT DESAT IN 4 6 6.8V CBLANK VDD 2 +22V 3 C Controller DD OUTSRC RH Gate and 1 FAULT Control OUTSNK 5 16 Logic RL VSS GATE 15 10 R OUTSOFT SOFT 14 SOURCE VDD VSS VREG INSOFT 4.6V 13 8 Regulator 2.6V V R1 DD C SET FLY Charge CAP CREG 9 Pump 12 Control RFLY CSS GND R2 11 COM 7 VSS
4.1 Logic Input (IN) 4.2 Gate Drive Outputs (OUTSRC and OUTSNK)
The logic input IN controls the state of the high current The IX4351NE power outputs are rated for 9A peak source driver output (OUTSRC), high current sink current capability. Separate source and sink outputs driver output (OUTSNK), and the lower current sink allow independent adjustment of the discrete SiC driver output (OUTSOFT). The IN input is a MOSFET or IGBT turn-on and turn-off transactions high-speed Schmitt trigger buffer with 0.4V hysteresis. with a single resistor. An internal dead time prevents The IN logic thresholds are TTL and CMOS cross conduction of the source and sink outputs. compatible, and are referenced to COM. When VDD is greater than the V
4.3 Internal 4.6V Regulator (VREG)
DD UVLO rising threshold (VDDUV+), typically 12V, IN controls the state of the gate driver The internal 4.6V regulator provides power for the low outputs according to Table 1: voltage control circuitry. An external 4.7F bypass capacitor (CREG) is required. VREG can source up to 4.1.1 Table 1 10mA, that can be used to set the negative bias
IN V
voltage and power an external logic optocoupler.
DD OUTSRC OUTSNK OUTSOFT
X < VDDUV+ Off Low Low 0 > VDDUV+ Off Low Low 1 > VDDUV+ High Off Off R02
www.ixysic.com
9 Document Outline Features Applications Description Ordering Information 1 Specifications 1.1 Package Pinout 1.2 Pin Description 1.3 Absolute Maximum Ratings 1.4 Recommended Operating Conditions 1.5 Electrical Characteristics 1.6 Thermal Characteristics 2 Performance Data 3 Performance Data (Cont.) 4 Functional Description 4.1 Logic Input (IN) 4.2 Gate Drive Outputs (OUTSRC and OUTSNK) 4.3 Internal 4.6V Regulator (VREG) 4.4 Negative VSS Charge Pump Regulator 4.5 Desaturation Detection and Protection 4.6 Thermal Shutdown 4.7 FAULT Output 5 Manufacturing Information 5.1 Moisture Sensitivity 5.2 ESD Sensitivity 5.3 Soldering Profile 5.4 Board Wash 5.5 Mechanical Dimensions
