Datasheet ADN8810 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 12-Bit High Output Current Source |
| Pages / Page | 14 / 9 — Data Sheet. ADN8810. TERMINOLOGY Relative Accuracy. Compliance Voltage. … |
| Revision | C |
| File Format / Size | PDF / 443 Kb |
| Document Language | English |
Data Sheet. ADN8810. TERMINOLOGY Relative Accuracy. Compliance Voltage. Output Current Change vs. Output Voltage Change
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Data Sheet ADN8810 TERMINOLOGY Relative Accuracy Compliance Voltage
Relative accuracy or integral nonlinearity (INL) is a measure of The maximum output voltage from the ADN8810 is a function the maximum deviation, in least significant bits (LSBs), from an of output current and supply voltage. Compliance voltage ideal line passing through the endpoints of the DAC transfer defines the maximum output voltage at a given current and function. Figure 4 shows a typical INL vs. code plot. The supply voltage to guarantee the device operates within its INL, ADN8810 INL is measured from 2% to 100% of the full-scale DNL, and gain error specifications. (FS) output.
Output Current Change vs. Output Voltage Change Differential Nonlinearity
This is a measure of the ADN8810 output impedance and is Differential nonlinearity (DNL) is the difference between the similar to a load regulation spec in voltage references. For a measured change and the ideal 1 LSB change between any two given code, the output current changes slightly as output voltage adjacent codes. A specified differential nonlinearity of ± 1 LSB increases. It is measured as an absolute value in (ppm of ful - maximum ensures monotonicity. The ADN8810 is guaranteed scale range)/V. monotonic by design. Figure 5 shows a typical DNL vs. code plot.
GAIN ERROR Offset Error PLUS
Offset error, or zero-code error, is an interpolation of the output
OFFSET ERROR
voltage at code 0x000 as predicted by the line formed from the
INTERPOLATED
output voltages at code 0x040 (2% FS) and code 0xFFF (100% FS). Ideal y, the offset error is 0 V. Offset error occurs from a
E AG
combination of the offset voltage of the amplifier and offset
LT O
errors in the DAC. It is expressed in LSBs.
T V IDEAL U Offset Drift TP OU
This is a measure of the change in offset error with a change in
ACTUAL
temperature. It is expressed in (ppm of ful -scale range)/°C.
(EXAGGERATED) Gain Error
Gain error is a measure of the span error of the DAC. It is the deviation in slope of the output transfer characteristic from ideal. The transfer characteristic is the line formed from the
OFFSET 0x040 0xFFF ERROR DAC CODE
output voltages at code 0x040 (2% FS) and code 0xFFF (100% FS). 004 0- It is expressed as a percent of the ful -scale range. 03195- Figure 16. Output Transfer Function Rev. C | Page 9 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY FUNCTIONAL DESCRIPTION SETTING FULL-SCALE OUTPUT CURRENT POWER SUPPLIES SERIAL DATA INTERFACE STANDBY AND RESET MODES POWER DISSIPATION USING MULTIPLE ADN8810 DEVICES FOR ADDITIONAL OUTPUT CURRENT ADDING DITHER TO THE OUTPUT CURRENT DRIVING COMMON-ANODE LASER DIODES PCB LAYOUT RECOMMENDATIONS SUGGESTED PAD LAYOUT FOR CP-24 PACKAGE OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADN8810 TERMINOLOGY Relative Accuracy Compliance Voltage
Relative accuracy or integral nonlinearity (INL) is a measure of The maximum output voltage from the ADN8810 is a function the maximum deviation, in least significant bits (LSBs), from an of output current and supply voltage. Compliance voltage ideal line passing through the endpoints of the DAC transfer defines the maximum output voltage at a given current and function. Figure 4 shows a typical INL vs. code plot. The supply voltage to guarantee the device operates within its INL, ADN8810 INL is measured from 2% to 100% of the full-scale DNL, and gain error specifications. (FS) output.
Output Current Change vs. Output Voltage Change Differential Nonlinearity
This is a measure of the ADN8810 output impedance and is Differential nonlinearity (DNL) is the difference between the similar to a load regulation spec in voltage references. For a measured change and the ideal 1 LSB change between any two given code, the output current changes slightly as output voltage adjacent codes. A specified differential nonlinearity of ± 1 LSB increases. It is measured as an absolute value in (ppm of ful - maximum ensures monotonicity. The ADN8810 is guaranteed scale range)/V. monotonic by design. Figure 5 shows a typical DNL vs. code plot.
GAIN ERROR Offset Error PLUS
Offset error, or zero-code error, is an interpolation of the output
OFFSET ERROR
voltage at code 0x000 as predicted by the line formed from the
INTERPOLATED
output voltages at code 0x040 (2% FS) and code 0xFFF (100% FS). Ideal y, the offset error is 0 V. Offset error occurs from a
E AG
combination of the offset voltage of the amplifier and offset
LT O
errors in the DAC. It is expressed in LSBs.
T V IDEAL U Offset Drift TP OU
This is a measure of the change in offset error with a change in
ACTUAL
temperature. It is expressed in (ppm of ful -scale range)/°C.
(EXAGGERATED) Gain Error
Gain error is a measure of the span error of the DAC. It is the deviation in slope of the output transfer characteristic from ideal. The transfer characteristic is the line formed from the
OFFSET 0x040 0xFFF ERROR DAC CODE
output voltages at code 0x040 (2% FS) and code 0xFFF (100% FS). 004 0- It is expressed as a percent of the ful -scale range. 03195- Figure 16. Output Transfer Function Rev. C | Page 9 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY FUNCTIONAL DESCRIPTION SETTING FULL-SCALE OUTPUT CURRENT POWER SUPPLIES SERIAL DATA INTERFACE STANDBY AND RESET MODES POWER DISSIPATION USING MULTIPLE ADN8810 DEVICES FOR ADDITIONAL OUTPUT CURRENT ADDING DITHER TO THE OUTPUT CURRENT DRIVING COMMON-ANODE LASER DIODES PCB LAYOUT RECOMMENDATIONS SUGGESTED PAD LAYOUT FOR CP-24 PACKAGE OUTLINE DIMENSIONS ORDERING GUIDE
