Preliminary Datasheet EPC2152 (Efficient Power Conversion) - 2

EPC2152 – 80 V, 12.5 A ePower™ Stage PRELIMINARY Functional Block Diagram
within 1 ns under ful load with PWM frequency up to 3 MHz. The charging path for the floating bootstrap supply is integrated using GaN FET driven by a synchronous circuit. This eliminates the need for an external bootstrap diode with associated reverse recovery charge that may result in significant power loss at high frequency switching. This synchronous bootstrap charging circuit also minimizes the voltage drop in the bootstrap charging path to ensure adequate voltage for the bootstrap power supply.
General Description
Robust level shifters from low side to high The EPC2152 is a single chip driver plus side channels are designed to operate eGaN® FET half-bridge power stage. correctly even at large negative clamped Integration is implemented using EPC’s voltage and to avoid false trigger from fast proprietary GaN IC technology. Input logic dv/dt transients exceeding 100 V/ns. interface, level shifting, bootstrap charging Internal regulation of the gate drive voltage and gate drive buffer circuits along with based on feedback from the driven output eGaN output FETs configured as a half- FETs ensures a safe gate voltage level while bridge are integrated within a monolithic stil turning on the output FETs to a low R chip. This results in a chip-scale LGA form DS(on) state. Additional protection is provided by factor device that measures only 3.85 mm x separate high side and low side under- 2.59 mm x 0.63 mm. voltage lockout (UVLO) circuits with lockout The two eGaN output FETs in half-bridge levels referenced to the gate drive buffer topology are designed to have same RDS(on). circuit to avoid operating the output FETs in Integration of eGaN FETs with on-chip gate a high RDS(on) state. drive buffers practically eliminate effects of The EPC2152 device is capable of interfacing common source inductance and gate drive to digital controllers that use standard 3.3 V loop inductance. Monolithic integration or 5V CMOS logic levels. Separate and combined with a pinout that uses low independent high side and low side logic inductance LGA solder bumps, result in a control inputs allow external controllers to high-current output node that can switch set deadtimes for optimal operating efficiency. Subject to Change without Notice www.epc-co.com COPYRIGHT 2020 Rev 1.1 Page 2