Preliminary Datasheet EPC2152 (Efficient Power Conversion) - 10

EPC2152 – 80 V, 12.5 A ePower™ Stage PRELIMINARY
Adjusting Switching Speed spike below ground for negative going edge during hard switching conditions, designers The EPC2152 device is designed to switch in less than 1 ns to minimize output FET can insert optional RDD resistor in series with the bias supply bypass capacitor C switching losses. Using the recommended DRV also shown in the same Test Circuit (Figure 1a). layout guidelines, shown in Figure 5 can The switching waveforms using different minimize the high frequency loop values of R inductance to less than 0.2 nH as BOOT on rising SW node are shown demonstrated in EPC90120 development in Figure 6a under the operating conditions of V board [2]. However, the fast di/dt at turn-on IN = 48 V, VOUT = 12 V and IOUT = 10 A. can induce a higher than acceptable over- Increasing RBOOT value helps to decrease switching speed, lower over-voltage spike voltage spike at the SW node. Designers can and reduce ringing. The power loss penalty is reduce the rise time of the SW node by inserting an optional R only 0.2% at IOUT = 10 A with RBOOT increasing BOOT resistor in series from 0 Ω to 20 Ω as shown in Figure 6b. The with the bootstrap bypass capacitor CBOOT as illustrated in Test Circuit for Dynamic associated peak over-rail voltage spike above V Characteristics (Figure 1a). This helps to IN of 48 V ranges from 35V over with R reduce over-voltage spike in the positive BOOT = 0 Ω to only 8 V over at RBOOT = 10 Ω going edge during hard switching conditions. (Figure 6a). At RBOOT = 20 Ω the waveform is critically damped. To reduce the negative transient voltage
Figure 6a: Switching Waveform Figure 6b: Efficiency Figure 6: Impact of RBOOT value on SW node switching characteristics, over-rail voltage spike and efficency for a buck converter operating from VIN = 48 V, VOUT = 12 V.
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