Datasheet KSZ8993M (Microchip) - 67
| Manufacturer | Microchip |
| Description | Integrated 3-Port 10/100 Managed Switch with PHYs |
| Pages / Page | 74 / 67 — KSZ8993M. 9.0. SELECTION OF ISOLATION TRANSFORMERS. TABLE 9-1:. … |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
KSZ8993M. 9.0. SELECTION OF ISOLATION TRANSFORMERS. TABLE 9-1:. TRANSFORMER SELECTION CRITERIA. Parameter. Value. Test Conditions
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KSZ8993M 9.0 SELECTION OF ISOLATION TRANSFORMERS
A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs exceeding FCC requirements. Table 9-1 lists recommended transformer characteristics.
TABLE 9-1: TRANSFORMER SELECTION CRITERIA Parameter Value Test Conditions
Turns Ratio 1 CT : 1 CT — Open-Circuit Inductance (min.) 350 μH 100 mV, 100 kHz, 8 mA Leakage Inductance (max.) 0.4 μH 1 MHz (min.) Interwinding Capacitance (max.) 12 pF — D.C. Resistance (max.) 0.9Ω — Insertion Loss (max.) 1.0 dB 0 MHz to 65 MHz HIPOT (min.) 1500 VRMS —
TABLE 9-2: QUALIFIED SINGLE-PORT MAGNETICS Manufacturer Part Number Auto MDI-X
Bel Fuse S558-5999-U7 Yes Bel Fuse (MagJack) SI-46001 Yes Bel Fuse (MagJack) SI-50170 Yes Delta LF8505 Yes LanKom LF-H41S Yes Pulse H1102 Yes Pulse (Low Cost) H1260 Yes Transpower HB726 Yes YCL LF-H41S Yes
TABLE 9-3: TYPICAL REFERENCE CRYSTAL CHARACTERISTICS Characteristic Value
Frequency 25 MHz Frequency Tolerance (max.) ±50 ppm Load Capacitance (max.) 20 pF Series Resistance 25Ω 2019 Microchip Technology Inc. DS00003066A-page 67 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 MAC and Switch 3.3 Advanced Switch Functions 3.4 Configuration Interface 3.5 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch and PHY (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-127) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MAC Mode MII Timing 7.4 PHY Mode MII Timing 7.5 SPI Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
KSZ8993M 9.0 SELECTION OF ISOLATION TRANSFORMERS
A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs exceeding FCC requirements. Table 9-1 lists recommended transformer characteristics.
TABLE 9-1: TRANSFORMER SELECTION CRITERIA Parameter Value Test Conditions
Turns Ratio 1 CT : 1 CT — Open-Circuit Inductance (min.) 350 μH 100 mV, 100 kHz, 8 mA Leakage Inductance (max.) 0.4 μH 1 MHz (min.) Interwinding Capacitance (max.) 12 pF — D.C. Resistance (max.) 0.9Ω — Insertion Loss (max.) 1.0 dB 0 MHz to 65 MHz HIPOT (min.) 1500 VRMS —
TABLE 9-2: QUALIFIED SINGLE-PORT MAGNETICS Manufacturer Part Number Auto MDI-X
Bel Fuse S558-5999-U7 Yes Bel Fuse (MagJack) SI-46001 Yes Bel Fuse (MagJack) SI-50170 Yes Delta LF8505 Yes LanKom LF-H41S Yes Pulse H1102 Yes Pulse (Low Cost) H1260 Yes Transpower HB726 Yes YCL LF-H41S Yes
TABLE 9-3: TYPICAL REFERENCE CRYSTAL CHARACTERISTICS Characteristic Value
Frequency 25 MHz Frequency Tolerance (max.) ±50 ppm Load Capacitance (max.) 20 pF Series Resistance 25Ω 2019 Microchip Technology Inc. DS00003066A-page 67 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 MAC and Switch 3.3 Advanced Switch Functions 3.4 Configuration Interface 3.5 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch and PHY (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-127) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MAC Mode MII Timing 7.4 PHY Mode MII Timing 7.5 SPI Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
