Datasheet ADE7816 (Analog Devices) - 4

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ADE7816 Data Sheet Parameter1, 2 Min Typ Max Unit Test Conditions/Comments
WAVEFORM SAMPLING Sampling CLKIN/2048, 16.384 MHz/2048 = 8 kSPS Current and Voltage Channels See the Instantaneous Waveforms section Signal-to-Noise Ratio, SNR 70 dB PGA = 1 Signal-to-Noise-and-Distortion Ratio, SINAD 60 dB PGA = 1 Bandwidth (−3 dB) 2 kHz TIME INTERVAL BETWEEN CHANNELS Measurement Error 0.3 Degrees Line frequency = 45 Hz to 65 Hz, HPF on REFERENCE INPUT REFIN/OUT Input Voltage Range 1.1 1.3 V Minimum = 1.2 V − 8%; maximum = 1.2 V + 8% Input Capacitance 10 pF ON-CHIP REFERENCE Nominal 1.207 V at the REFIN/OUT pin at TA = 25°C Reference Error ±2 mV Output Impedance 1.2 kΩ Temperature Coefficient 10 50 ppm/°C Maximum value across full temperature range of −40°C to +85°C CLKIN, CLKOUT All specifications are for CLKIN, CLKOUT of 16.384 MHz Input Clock Frequency 16.22 16.384 16.55 MHz LOGIC INPUTS—MOSI/SDA, SCLK/SCL, SS/HSA, RESET, PULL_HIGH, PULL_LOW Input High Voltage, VINH 2.0 V VDD = 3.3 V ± 10% Input Low Voltage, VINL 0.8 V VDD = 3.3 V ± 10% Input Current, IIN −8.7 µA Input = 0 V, VDD = 3.3 V 3 μA Input = VDD = 3.3 V 100 nA Input = VDD = 3.3 V Input Capacitance, CIN 10 pF LOGIC OUTPUTS—IRQ0, IRQ1, MISO/HSD VDD = 3.3 V ± 10% Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 10% ISOURCE 800 µA Output Low Voltage, VOL 0.4 V VDD = 3.3 V ± 10% ISINK 2 mA POWER SUPPLY For specified performance VDD Pin 3.0 3.6 V Minimum = 3.3 V − 10%; maximum = 3.3 V + 10% IDD 25 27.8 mA 1 See the Typical Performance Characteristics section. 2 See the Terminology section for a definition of the parameters. Rev. B | Page 4 of 48 Document Outline Features General Description Functional Block Diagram Revision History Specifications Timing Characteristics I2C-Compatible Interface Timing SPI Interface Timing HSDC Interface Timing Load Circuit for All Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuit Terminology Quick Start Inputs Power and Ground VDD and AGND, DGND Reference Circuit REFIN/OUT Reset Hardware Reset Software Reset Functionality CLKIN and CLKOUT Analog Inputs Input Pins PGA Gain Digital Integrator Antialiasing Filters Energy Measurements Starting and Stopping the DSP Active Energy Measurement Definition of Active Power and Active Energy Active Energy Registers Active Energy Threshold Energy Accumulation and Register Roll-Over Reactive Energy Measurement Definition of Reactive Power and Reactive Energy Reactive Energy Registers Reactive Energy Threshold Reactive Energy Accumulation and Register Roll-Over Line Cycle Accumulation Mode Root Mean Square Measurement No Load Detection Setting the No Load Thresholds No Load Interrupt Energy Calibration Channel Matching Energy Gain Calibration Energy Offset Calibration Energy Phase Calibration RMS Offset Calibration Power Quality Features Selecting a Current Channel Group Instantaneous Waveforms Zero-Crossing Detection Zero-Crossing Detection Zero-Crossing Timeout Peak Detection Setting the PEAKCYC Register Overcurrent and Overvoltage Detection Setting the OVLVL and OILVL Registers Overvoltage and Overcurrent Interrupts Indication of Power Direction Angle Measurements Period Measurement Voltage Sag Detection Setting the SAGCYC Register Setting the SAGLVL Register Voltage Sag Interrupt Checksum Layout Guidelines Crystal Circuit Outputs Interrupts Communication Serial Interface Selection I2C-Compatible Interface I2C Write Operation I2C Read Operation SPI-Compatible Interface SPI Read Operation SPI Write Operation HSDC Interface Registers Register Protection Register Format Register Maps Register Descriptions Interrupt Enable and Interrupt Status Registers Outline Dimensions Ordering Guide