Datasheet AD74413R (Analog Devices) - 67

Data Sheet AD74413R ALERT MASK REGISTER Address: 0x3C, Reset: 0x0000, Name: ALERT_MASK
This register masks the alert status bits, outlined in the ALERT_STATUS register, from activating the ALERT pin. The position of mask bits in this register line up with the corresponding status bits in the ALERT_STATUS register.
Table 47. Bit Descriptions for ALERT_MASK Bits Bit Name Description Reset Access
15 RESERVED Reserved. 0x0 R 14 CAL_MEM_ERR_MASK Mask bit for the CAL_MEM_ERR bit. 0x0 R/W 13 SPI_CRC_ERR_MASK Mask bit for the SPI_CRC_ERR bit. 0x0 R/W 12 SPI_SCLK_CNT_ERR_MASK Mask bit for the SPI_SCLK_CNT_ERR bit. 0x0 R/W 11 ADC_SAT_ERR_MASK Mask bit for the ADC_SAT_ERR bit. 0x0 R/W 10 ADC_CONV_ERR_MASK Mask bit for the ADC_CONV_ERR bit. 0x0 R/W 9 ALDO1V8_ERR_MASK Mask bit for the ALDO1V8_ERR bit. 0x0 R/W 8 DVCC_ERR_MASK Mask bit for the DVCC_ERR bit. 0x0 R/W 7 AVDD_ERR_MASK Mask bit for the AVDD_ERR bit. 0x0 R/W 6 ALDO5V_ERR_MASK Mask bit for the ALDO5V_ERR bit. 0x0 R/W 5 CHARGE_PUMP_ERR_MASK Mask bit for the CHARGE_PUMP_ERR bit. 0x0 R/W 4 HI_TEMP_ERR_MASK Mask bit for the HI_TEMP_ERR bit. 0x0 R/W 3 VI_ERR_MASK_D Mask bit for the VI_ERR_D bit. 0x0 R/W 2 VI_ERR_MASK_C Mask bit for the VI_ERR_C bit. 0x0 R/W 1 VI_ERR_MASK_B Mask bit for the VI_ERR_B bit. 0x0 R/W 0 VI_ERR_MASK_A Mask bit for the VI_ERR_A bit. 0x0 R/W
DEBOUNCED DIN COUNT REGISTER PER CHANNEL Address: 0x3D to 0x40 (Increments of 0x01), Reset: 0x0000, Name: DIN_COUNTERx
This counter is enabled when the COUNT_EN bit in DIN_CONFIGx register is set. The INV_DIN_COMP_OUT bit inverts the deglitched output, allowing the counter increment edge to be modified.
Table 48. Bit Descriptions for DIN_COUNTERx Bits Bit Name Description Reset Access
[15:0] DIN_CNT This counter is enabled when the COUNT_EN bit in the DIN_CONFIGx register is set. The count is 0x0 R frozen when the enable signal is low. This counter value rolls over from full scale back to 0. Therefore, read this register often enough to avoid unexpected roll over. When INV_DIN_COMP_OUT is set to 0, the counter increments on the rising digital input edges. When INV_DIN_COMP_OUT is set to 1, the counter increments on the falling digital input edges. Rev. 0 | Page 67 of 70 Document Outline Features Applications General Description Companion Products Product Highlights Revision History Functional Block Diagram Specifications Voltage Output Current Output Voltage Input Current Input Externally Powered and Current Input Externally Powered with HART Current Input Loop Powered Resistance Measurement Digital Input Logic Digital Input Loop Powered ADC Specifications General Specifications Timing Characteristics SPI Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Voltage Output Current Output Digital Input Resistance Measurement Reference ADC Supplies Theory of Operation Robust Architecture Serial Interface DAC Architecture ADC Overview Reference Reference Noise Charge Pump Power-On State of the AD74413R Device Functions High Impedance Interpreting ADC Data Voltage Output Mode Voltage Output Short-Circuit Protection Interpreting ADC Data Current Output Mode Current Output Open Circuit Detection Interpreting ADC Data HART Compatibility Voltage Input Mode Selectable 200 kΩ to GND Interpreting ADC Data Thermocouple Measurement Current Input, Externally Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Externally Powered with HART Compatibility Mode Current Input, Loop Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Loop Powered with HART Compatibility Mode Resistance Measurement (External 2-Wire RTD) Interpreting ADC Data Digital Input Logic Interpreting ADC Data Digital Input Threshold Setting Digital Input Current Sink Debounce Function Debounce Mode 0 (Default) Debounce Mode 1 Digital Input Inverter Digital Input Counter Digital Input, Loop Powered Mode Interpreting ADC Data Getting Started Using Channel Functions Switching Channel Functions ADC Functionality ADC Conversion Rates ADC_RDYb Functionality ADC Output Data Format ADC Noise Diagnostics DACs LDAC Function Clear Code Function Digital Linear Slew Rate Control HART Compliant Slew Driving Inductive Loads Reset Function Thermal Alert and Thermal Reset Faults and Alerts Channel Faults Power Supply Monitors GPO_x Pins SPI Interface and Diagnostics SPI CRC SPI Interface SCLK Count Feature Readback Mode Streaming Mode Auto Readback Board Design and Layout Considerations Applications Information Register Map NOP Register Function Setup Register per Channel ADC Configuration Register per Channel Digital Input Configuration Register per Channel GPO Parallel Data Register GPO Configuration Register per Channel Output Configuration Register per Channel DAC Code Register per Channel DAC Clear Code Register per Channel DAC Active Code Register per Channel Digital Input Threshold Register ADC Conversion Control Register Diagnostics Select Register Digital Output Level Register ADC Conversion Results Register per Channel Diagnostic Results Registers per Diagnostic Channel Alert Status Register Live Status Register Alert Mask Register Debounced DIN Count Register per Channel Readback Select Register Thermal Reset Enable Register Command Register Scratch or Spare Register Silicon Revision Register Outline Dimensions Ordering Guide