Datasheet AD5590 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 16 Input, 16 Output Analog I/O Port with Integrated Amplifiers |
| Pages / Page | 44 / 9 — AD5590. TIMING SPECIFICATIONS ADC Timing Characteristics. Table 5. … |
| Revision | A |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
AD5590. TIMING SPECIFICATIONS ADC Timing Characteristics. Table 5. Parameter. Limit at TMIN, TMAX; ADCVDD = 5 V Unit
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AD5590 TIMING SPECIFICATIONS ADC Timing Characteristics
ADCVDD = 2.7 V to 5.25 V, VDRIVE ≤ ADCVDD, VREFA = 2.5 V; All specifications TMIN to TMAX, unless otherwise noted.
Table 5. Parameter
1
Limit at TMIN, TMAX; ADCVDD = 5 V Unit Conditions/Comments
f 2 SCLK 10 kHz min 20 MHz min tCONVERT 16 × tASCLK MHz max tQUIET 50 ns min t2 10 ns min ASYNC to ASCLK setup time t 3 3 14 ns max Delay from ASYNC until ADOUT three-state disabled t3b4 20 ns min Data hold time t 3 4 40 ns max Data access time after ASCLK falling edge t5 0.4 × tASCLK ns min ASCLK low pulse width t6 0.4 × tASCLK ns min ASCLK high pulse width t7 15 ns min ASCLK to ADOUT valid hold time t 5 8 15/50 ns min/max ASCLK falling edge to ADOUT high impedance t9 20 ns min ADIN setup time prior to ASCLK falling edge t10 5 ns min ADIN Hold time prior to ASCLK falling edge t11 20 ns min 16th ASCLK falling edge to ASYNC high t12 1 µs max Power-up time from full power-down/autoshutdown/ autostandby modes 1 Guaranteed by design and characterization. Not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of ADCVDD) and timed from a voltage level of 1.6 V. 2 Maximum ASCLK frequency is 50 MHz at ADCVDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested. 3 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE. 4 t3b represents a worst-case figure for having ADD3 available on the ADOUT line, that is, if the ADC goes back into three-state at the end of a conversion and some other device takes control of the bus between conversions, the user needs to wait a maximum time of t3b before having ADD3 valid on the ADOUT line. If the ADOUT line is weakly driven to ADD3 between conversions, then the user typically needs to wait 17 ns at 3 V and 12 ns at 5 V after the ASYNC falling edge before seeing ADD3 valid on ADOUT. 5 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of bus loading.
ASYNC B tCONVERT t2 t6 ASCLK 1 2 3 4 5 6 13 14 15 16 t3b t t4 t7 t5 t11 3 tQUIET ADOUT ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0 THREE- THREE- STATE t ADD3 9 FOUR IDENTIFICATION BITS t10 t8 STATE
002
ADIN WRITE SEQ ADD3 ADD2 ADD1 ADD0 DONTC DONTC DONTC
07691- Figure 2. ADC Timing Characteristics
200µA IOL TO OUTPUT 1.6V PIN CL 25pF
003
200µA IOH
07691- Figure 3. Load Circuit for ADC Digital Output Timing Specifications Rev. A | Page 9 of 44 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications ADC Specifications DAC Specifications DAC AC Characteristics Operational Amplifier Specifications Timing Specifications ADC Timing Characteristics DAC Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics DAC ADC Amplifier Terminology Theory of Operation DAC Section Resistor String DAC Internal Reference DAC Output Amplifier ADC Section ADC Converter Operation Analog Input ADC Transfer Function Analog Input Selection Digital Inputs VDRIVE Reference Section Amplifier Section Serial Interface Accessing the DAC Block DAC Input Shift Register Interrupt DAC Internal Reference Register DAC Power-On Reset DAC Power-Down Modes DAC Clear Code Register LDAC Function Accessing the ADC Block ADC Modes of Operation Normal Mode (PM1 = PM0 = 1) Full Shutdown (PM1 = 1, PM0 = 0) AutoShutdown (PM1 = 0, PM0 = 1) Autostandby (PM1 = PM0 = 0) Powering Up the ADC Interfacing to the ADC ADC Control Register ADC Sequencer Operation ADC Shadow Register ADC Power vs. Throughput Rate Outline Dimensions Ordering Guide
AD5590 TIMING SPECIFICATIONS ADC Timing Characteristics
ADCVDD = 2.7 V to 5.25 V, VDRIVE ≤ ADCVDD, VREFA = 2.5 V; All specifications TMIN to TMAX, unless otherwise noted.
Table 5. Parameter
1
Limit at TMIN, TMAX; ADCVDD = 5 V Unit Conditions/Comments
f 2 SCLK 10 kHz min 20 MHz min tCONVERT 16 × tASCLK MHz max tQUIET 50 ns min t2 10 ns min ASYNC to ASCLK setup time t 3 3 14 ns max Delay from ASYNC until ADOUT three-state disabled t3b4 20 ns min Data hold time t 3 4 40 ns max Data access time after ASCLK falling edge t5 0.4 × tASCLK ns min ASCLK low pulse width t6 0.4 × tASCLK ns min ASCLK high pulse width t7 15 ns min ASCLK to ADOUT valid hold time t 5 8 15/50 ns min/max ASCLK falling edge to ADOUT high impedance t9 20 ns min ADIN setup time prior to ASCLK falling edge t10 5 ns min ADIN Hold time prior to ASCLK falling edge t11 20 ns min 16th ASCLK falling edge to ASYNC high t12 1 µs max Power-up time from full power-down/autoshutdown/ autostandby modes 1 Guaranteed by design and characterization. Not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of ADCVDD) and timed from a voltage level of 1.6 V. 2 Maximum ASCLK frequency is 50 MHz at ADCVDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested. 3 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE. 4 t3b represents a worst-case figure for having ADD3 available on the ADOUT line, that is, if the ADC goes back into three-state at the end of a conversion and some other device takes control of the bus between conversions, the user needs to wait a maximum time of t3b before having ADD3 valid on the ADOUT line. If the ADOUT line is weakly driven to ADD3 between conversions, then the user typically needs to wait 17 ns at 3 V and 12 ns at 5 V after the ASYNC falling edge before seeing ADD3 valid on ADOUT. 5 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of bus loading.
ASYNC B tCONVERT t2 t6 ASCLK 1 2 3 4 5 6 13 14 15 16 t3b t t4 t7 t5 t11 3 tQUIET ADOUT ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0 THREE- THREE- STATE t ADD3 9 FOUR IDENTIFICATION BITS t10 t8 STATE
002
ADIN WRITE SEQ ADD3 ADD2 ADD1 ADD0 DONTC DONTC DONTC
07691- Figure 2. ADC Timing Characteristics
200µA IOL TO OUTPUT 1.6V PIN CL 25pF
003
200µA IOH
07691- Figure 3. Load Circuit for ADC Digital Output Timing Specifications Rev. A | Page 9 of 44 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications ADC Specifications DAC Specifications DAC AC Characteristics Operational Amplifier Specifications Timing Specifications ADC Timing Characteristics DAC Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics DAC ADC Amplifier Terminology Theory of Operation DAC Section Resistor String DAC Internal Reference DAC Output Amplifier ADC Section ADC Converter Operation Analog Input ADC Transfer Function Analog Input Selection Digital Inputs VDRIVE Reference Section Amplifier Section Serial Interface Accessing the DAC Block DAC Input Shift Register Interrupt DAC Internal Reference Register DAC Power-On Reset DAC Power-Down Modes DAC Clear Code Register LDAC Function Accessing the ADC Block ADC Modes of Operation Normal Mode (PM1 = PM0 = 1) Full Shutdown (PM1 = 1, PM0 = 0) AutoShutdown (PM1 = 0, PM0 = 1) Autostandby (PM1 = PM0 = 0) Powering Up the ADC Interfacing to the ADC ADC Control Register ADC Sequencer Operation ADC Shadow Register ADC Power vs. Throughput Rate Outline Dimensions Ordering Guide
