Datasheet ADuM6420A, ADuM6421A, ADuM6422A (Analog Devices) - 26
| Manufacturer | Analog Devices |
| Description | Quad-Channel Isolators with Integrated DC-to-DC Converter |
| Pages / Page | 29 / 26 — ADuM6420A/. ADuM6421A. /ADuM6422A. Data Sheet. APPLICATIONS INFORMATION. … |
| File Format / Size | PDF / 661 Kb |
| Document Language | English |
ADuM6420A/. ADuM6421A. /ADuM6422A. Data Sheet. APPLICATIONS INFORMATION. PCB LAYOUT. Table 31. Surface-Mount Ferrite Beads Example
Model Line for this Datasheet
Text Version of Document
link to page 26 link to page 26 link to page 26 link to page 26 link to page 26 link to page 16
ADuM6420A/ ADuM6421A /ADuM6422A Data Sheet APPLICATIONS INFORMATION PCB LAYOUT
To reduce the level of electromagnetic radiation, the impedance The ADuM6420A/ADuM6421A/ADuM6422A digital isolators to high frequency currents between the VISO and the GNDISO with an isoPower integrated dc-to-dc converter require no pins and the PCB trace connections can be increased. Using this external interface circuitry for the logic interfaces. Power supply method of electromagnetic interference (EMI) suppression bypassing is required at the input and output supply pins (see controls the radiating signal at the signal source by placing Figure 21, Figure 22 and Figure 23). For proper operation of the surface-mount ferrite beads in series with the VISO and GNDISO data channels, low equivalent series resistance (ESR) bypass pins, as seen in Figure 23. The impedance of the ferrite bead capacitors of 0.01 µF to 0.1 µF are required between the V must be approximately 1.8 kΩ between the 100 MHz and 1 GHz DD1 pin and GND frequency range to reduce the emissions at the 180 MHz 1 pin and between the VDD2 pin and GND2 pin as close to the chip pads as possible. Installing the bypass capacitor primary switching frequency and the 360 MHz secondary side, with traces more than 2 mm in length may result in data rectifying frequency and harmonics. See Table 31 for examples corruption. The isoPower inputs require several passive of appropriate surface-mount ferrite beads. components to bypass the power effectively, as well as set the
Table 31. Surface-Mount Ferrite Beads Example
output voltage.
Manufacturer Part No. VDD1
Taiyo Yuden BKH1005LM182-T
1 GND1
Murata Electronics BLM15HD182SN1
2 ADuM6420A PDIS 9 ADuM6421A BYPASS <2mm GND1 ADuM6422A 10 0.1µF 0.1µF V V V DDP DD1 DD2 11 GND1 GND2 GND1 10µF 0.1µF 12 GND1 GND2
025
VIA VOA V V
21365-
IB OB
Figure 21. V
V VOC/VIC
DD1 and VDDP Bias and Bypass Components
IC/VOC V V ID/VOD OD/VID V GND DD2 GND1 2 28 VSEL 0.1µF PDIS GND2 27 GND1 GNDISO VDDP VISO VSEL 20 GND1 GNDISO 10µF 0.1µF 0.1µF FERRITES 10µF GND NIC ISO 19
027
GND1 GNDISO V FB1 ISO
21365-
18 VISO OUT GND
Figure 23. Recommended PCB Layout
ISO 0.1µF 10µF 17 FB2
In applications involving high common-mode transients, ensure
ISO GND
026 21365- that board coupling across the isolation barrier is minimized. Figure 22. VDD2 and VISO Bias and Bypass Components Furthermore, design the board layout such that any coupling The power supply section of the ADuM6420A/ADuM6421A/ that does occur equal y affects all pins on a given component ADuM6422A use a 180 MHz oscil ator frequency to efficiently side. Failure to ensure these steps can cause voltage differentials pass power through the chip scale transformers. Bypass capacitors between pins, exceeding the absolute maximum ratings specified are required for several operating frequencies. Noise suppression in Table 24, thereby leading to latch-up and/or permanent requires a low inductance, high frequency capacitor. Ripple damage. suppression and proper regulation require a large value capacitor. These capacitors are connected between the VDDP pin and GND1 pin and between the VISO pin and GNDISO pin. To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The required capacitor values are 0.1 µF and 10 µF for VDD1. The smaller capacitor must have a low ESR. For example, use of a ceramic capacitor is advised. The total lead length between the ends of the low ESR capacitor and the input power supply pin must not exceed 2 mm. Rev. 0 | Page 26 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—3.3 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY ELECTRICAL CHARACTERISTICS—2.5 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY ELECTRICAL CHARACTERISTICS—1.8 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY PACKAGE CHARACTERISTICS REGULATORY APPROVALS INSULATION AND SAFETY RELATED SPECIFICATIONS DIN V VDE V 0884-11 INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TRUTH TABLE TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION APPLICATIONS INFORMATION PCB LAYOUT THERMAL ANALYSIS PROPAGATION DELAY RELATED PARAMETERS EMI CONSIDERATIONS POWER CONSUMPTION INSULATION LIFETIME Surface Tracking Insulation Wear Out Calculation and Use of Parameters Example OUTLINE DIMENSIONS ORDERING GUIDE
ADuM6420A/ ADuM6421A /ADuM6422A Data Sheet APPLICATIONS INFORMATION PCB LAYOUT
To reduce the level of electromagnetic radiation, the impedance The ADuM6420A/ADuM6421A/ADuM6422A digital isolators to high frequency currents between the VISO and the GNDISO with an isoPower integrated dc-to-dc converter require no pins and the PCB trace connections can be increased. Using this external interface circuitry for the logic interfaces. Power supply method of electromagnetic interference (EMI) suppression bypassing is required at the input and output supply pins (see controls the radiating signal at the signal source by placing Figure 21, Figure 22 and Figure 23). For proper operation of the surface-mount ferrite beads in series with the VISO and GNDISO data channels, low equivalent series resistance (ESR) bypass pins, as seen in Figure 23. The impedance of the ferrite bead capacitors of 0.01 µF to 0.1 µF are required between the V must be approximately 1.8 kΩ between the 100 MHz and 1 GHz DD1 pin and GND frequency range to reduce the emissions at the 180 MHz 1 pin and between the VDD2 pin and GND2 pin as close to the chip pads as possible. Installing the bypass capacitor primary switching frequency and the 360 MHz secondary side, with traces more than 2 mm in length may result in data rectifying frequency and harmonics. See Table 31 for examples corruption. The isoPower inputs require several passive of appropriate surface-mount ferrite beads. components to bypass the power effectively, as well as set the
Table 31. Surface-Mount Ferrite Beads Example
output voltage.
Manufacturer Part No. VDD1
Taiyo Yuden BKH1005LM182-T
1 GND1
Murata Electronics BLM15HD182SN1
2 ADuM6420A PDIS 9 ADuM6421A BYPASS <2mm GND1 ADuM6422A 10 0.1µF 0.1µF V V V DDP DD1 DD2 11 GND1 GND2 GND1 10µF 0.1µF 12 GND1 GND2
025
VIA VOA V V
21365-
IB OB
Figure 21. V
V VOC/VIC
DD1 and VDDP Bias and Bypass Components
IC/VOC V V ID/VOD OD/VID V GND DD2 GND1 2 28 VSEL 0.1µF PDIS GND2 27 GND1 GNDISO VDDP VISO VSEL 20 GND1 GNDISO 10µF 0.1µF 0.1µF FERRITES 10µF GND NIC ISO 19
027
GND1 GNDISO V FB1 ISO
21365-
18 VISO OUT GND
Figure 23. Recommended PCB Layout
ISO 0.1µF 10µF 17 FB2
In applications involving high common-mode transients, ensure
ISO GND
026 21365- that board coupling across the isolation barrier is minimized. Figure 22. VDD2 and VISO Bias and Bypass Components Furthermore, design the board layout such that any coupling The power supply section of the ADuM6420A/ADuM6421A/ that does occur equal y affects all pins on a given component ADuM6422A use a 180 MHz oscil ator frequency to efficiently side. Failure to ensure these steps can cause voltage differentials pass power through the chip scale transformers. Bypass capacitors between pins, exceeding the absolute maximum ratings specified are required for several operating frequencies. Noise suppression in Table 24, thereby leading to latch-up and/or permanent requires a low inductance, high frequency capacitor. Ripple damage. suppression and proper regulation require a large value capacitor. These capacitors are connected between the VDDP pin and GND1 pin and between the VISO pin and GNDISO pin. To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The required capacitor values are 0.1 µF and 10 µF for VDD1. The smaller capacitor must have a low ESR. For example, use of a ceramic capacitor is advised. The total lead length between the ends of the low ESR capacitor and the input power supply pin must not exceed 2 mm. Rev. 0 | Page 26 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—3.3 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY ELECTRICAL CHARACTERISTICS—2.5 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY ELECTRICAL CHARACTERISTICS—1.8 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY PACKAGE CHARACTERISTICS REGULATORY APPROVALS INSULATION AND SAFETY RELATED SPECIFICATIONS DIN V VDE V 0884-11 INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TRUTH TABLE TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION APPLICATIONS INFORMATION PCB LAYOUT THERMAL ANALYSIS PROPAGATION DELAY RELATED PARAMETERS EMI CONSIDERATIONS POWER CONSUMPTION INSULATION LIFETIME Surface Tracking Insulation Wear Out Calculation and Use of Parameters Example OUTLINE DIMENSIONS ORDERING GUIDE
