Datasheet LTM4650A (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Dual 25A or Single 50A DC/DC μModule Regulator with 1% DC Accuracy |
| Pages / Page | 38 / 9 — PIN FUNCTIONS (Recommended to Use Test Points to Monitor Signal Pin … |
| File Format / Size | PDF / 2.3 Mb |
| Document Language | English |
PIN FUNCTIONS (Recommended to Use Test Points to Monitor Signal Pin Connections.)
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LTM4650A
PIN FUNCTIONS (Recommended to Use Test Points to Monitor Signal Pin Connections.) PACKAGE ROW AND COLUMN LABELING MAY VARY TRACK1, TRACK2 (E5, D8):
Output Voltage Tracking Pin
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
and Soft-Start Inputs. Each channel has a 1.3µA pull-up
LAYOUT CAREFULLY.
current source. When one channel is configured to be
VOUT1 (A1–A5, B1–B5, C1–C4):
Power Output Pins. Apply master of the two channels, then a capacitor from this pin output load between these pins and GND pins. Recommend to ground will set a soft-start ramp rate. The remaining placing output decoupling capacitance directly between channel can be set up as the slave, and have the master’s these pins and GND pins. Review Table 6. output applied through a voltage divider to the slave out-
GND (A6–A7, B6–B7, D1–D4, D9–D12, E1–E4, E10–E12,
put’s track pin. This voltage divider is equal to the slave
F1–F3, F10–F12, G1, G3, G10, G12, H1–H7, H9–H12,
output’s feedback divider for coincidental tracking. See
J1, J5, J8, J12, K1, K5–K8, K12, L1, L12, M1 , M12):
the Applications Information section. Power Ground Pins for Both Input and Output Returns.
COMP1, COMP2 (E6, E7):
Current control threshold and
VOUT2 (A8–A12, B8–B12, C9–C12):
Power Output Pins. error amplifier compensation point for each channel. The Apply output load between these pins and GND pins. Rec- current comparator threshold increases with this control ommend placing output decoupling capacitance directly voltage. This device is internal compensated. See Applica- between these pins and GND pins. Review Table 6. tions Information section. Tie the COMP pins together for
V
parallel operation. Do not drive this pin.
OUTS1, VOUTS2 (C5, C8):
This pin is connected to the top of the internal top feedback resistor for each output. The
DIFFP (E8):
Positive input of the remote sense amplifier. pin can be directly connected to its specific output, or This pin is connected to the remote sense point of the connected to DIFFOUT when the remote sense amplifier output voltage. Diffamp can be used for ≤3.3V outputs. is used. In paralleling modules, one of the VOUTS pins is See the Applications Information section. connected to the DIFFOUT pin in remote sensing or directly to V
DIFFN (E9):
Negative input of the remote sense amplifier. OUT with no remote sensing. It is very important to connect these pins to either the DIFFOUT or V This pin is connected to the remote sense point of the OUT since this is the feedback path, and cannot be left open. See the output GND. Diffamp can be used for ≤3.3V outputs. See Applications Information section. the Applications Information section.
f MODE_PLLIN (F4):
Force Continuous Mode, Burst Mode
SET (C6):
Frequency Set Pin. A 10µA current is sourced from this pin. A resistor from this pin to ground sets a Operation, or Pulse-Skipping Mode Selection Pin and voltage that in turn programs the operating frequency. External Synchronization Input to Phase Detector Pin. Alternatively, this pin can be driven with a DC voltage Connect this pin to SGND to force both channels into that can set the operating frequency. See the Applications force continuous mode of operation. Connect to INTVCC Information section. to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on
SGND (C7, D6, G6–G7, F6–F7):
Signal Ground Pin. Return the pin will force both channels into continuous mode of ground path for all analog and low power circuitry. Tie a operation and synchronized to the external clock applied single connection to the output capacitor GND in the ap- to this pin. plication. See layout guidelines in Figure 13.
RUN1, RUN2 (F5, F9):
Run Control Pin. A voltage above
VFB1, VFB2 (D5, D7):
The Negative Input of the Error Am- 1.25V will turn on each channel in the module. A voltage plifier for Each Channel. Internally, this pin is connected below 1.25V on the RUN pin will turn off the related chan- to VOUTS1 or VOUTS2 with a 60.4kΩ precision resistor. nel. Each RUN pin has a 1µA pull-up current, once the Different output voltages can be programmed with an ad- RUN pin reaches 1.2V an additional 4.5µA pull-up current ditional resistor between VFB and GND pins. In PolyPhase® is added to this pin. operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. Do not drive this pin. 4650afb For more information www.linear.com/LTM4650A 9
PIN FUNCTIONS (Recommended to Use Test Points to Monitor Signal Pin Connections.) PACKAGE ROW AND COLUMN LABELING MAY VARY TRACK1, TRACK2 (E5, D8):
Output Voltage Tracking Pin
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
and Soft-Start Inputs. Each channel has a 1.3µA pull-up
LAYOUT CAREFULLY.
current source. When one channel is configured to be
VOUT1 (A1–A5, B1–B5, C1–C4):
Power Output Pins. Apply master of the two channels, then a capacitor from this pin output load between these pins and GND pins. Recommend to ground will set a soft-start ramp rate. The remaining placing output decoupling capacitance directly between channel can be set up as the slave, and have the master’s these pins and GND pins. Review Table 6. output applied through a voltage divider to the slave out-
GND (A6–A7, B6–B7, D1–D4, D9–D12, E1–E4, E10–E12,
put’s track pin. This voltage divider is equal to the slave
F1–F3, F10–F12, G1, G3, G10, G12, H1–H7, H9–H12,
output’s feedback divider for coincidental tracking. See
J1, J5, J8, J12, K1, K5–K8, K12, L1, L12, M1 , M12):
the Applications Information section. Power Ground Pins for Both Input and Output Returns.
COMP1, COMP2 (E6, E7):
Current control threshold and
VOUT2 (A8–A12, B8–B12, C9–C12):
Power Output Pins. error amplifier compensation point for each channel. The Apply output load between these pins and GND pins. Rec- current comparator threshold increases with this control ommend placing output decoupling capacitance directly voltage. This device is internal compensated. See Applica- between these pins and GND pins. Review Table 6. tions Information section. Tie the COMP pins together for
V
parallel operation. Do not drive this pin.
OUTS1, VOUTS2 (C5, C8):
This pin is connected to the top of the internal top feedback resistor for each output. The
DIFFP (E8):
Positive input of the remote sense amplifier. pin can be directly connected to its specific output, or This pin is connected to the remote sense point of the connected to DIFFOUT when the remote sense amplifier output voltage. Diffamp can be used for ≤3.3V outputs. is used. In paralleling modules, one of the VOUTS pins is See the Applications Information section. connected to the DIFFOUT pin in remote sensing or directly to V
DIFFN (E9):
Negative input of the remote sense amplifier. OUT with no remote sensing. It is very important to connect these pins to either the DIFFOUT or V This pin is connected to the remote sense point of the OUT since this is the feedback path, and cannot be left open. See the output GND. Diffamp can be used for ≤3.3V outputs. See Applications Information section. the Applications Information section.
f MODE_PLLIN (F4):
Force Continuous Mode, Burst Mode
SET (C6):
Frequency Set Pin. A 10µA current is sourced from this pin. A resistor from this pin to ground sets a Operation, or Pulse-Skipping Mode Selection Pin and voltage that in turn programs the operating frequency. External Synchronization Input to Phase Detector Pin. Alternatively, this pin can be driven with a DC voltage Connect this pin to SGND to force both channels into that can set the operating frequency. See the Applications force continuous mode of operation. Connect to INTVCC Information section. to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on
SGND (C7, D6, G6–G7, F6–F7):
Signal Ground Pin. Return the pin will force both channels into continuous mode of ground path for all analog and low power circuitry. Tie a operation and synchronized to the external clock applied single connection to the output capacitor GND in the ap- to this pin. plication. See layout guidelines in Figure 13.
RUN1, RUN2 (F5, F9):
Run Control Pin. A voltage above
VFB1, VFB2 (D5, D7):
The Negative Input of the Error Am- 1.25V will turn on each channel in the module. A voltage plifier for Each Channel. Internally, this pin is connected below 1.25V on the RUN pin will turn off the related chan- to VOUTS1 or VOUTS2 with a 60.4kΩ precision resistor. nel. Each RUN pin has a 1µA pull-up current, once the Different output voltages can be programmed with an ad- RUN pin reaches 1.2V an additional 4.5µA pull-up current ditional resistor between VFB and GND pins. In PolyPhase® is added to this pin. operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. Do not drive this pin. 4650afb For more information www.linear.com/LTM4650A 9
