Datasheet LTM4625 (Analog Devices) - 9

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APPLICATIONS INFORMATION
The typical LTM4625 application circuit is shown in For parallel operation of N channels, use the following Figure 20. External component selection is primarily equation to solve for RFB. Tie the VOUT, the COMP and FB determined by the input voltage, the output voltage pins together for each paralleled output. Connect a single and the maximum load current. Refer to Table 7 for resistor from FB to GND as determined by: specific external capacitor requirements for a particular application. 0.6V 60.4k RFB = • V N
V
OUT – 0.6V
IN to VOUT Step-Down Ratios
There are restrictions in the maximum VIN and VOUT step- See Figure 23 for an example of parallel operation. down ratios that can be achieved for a given input voltage due to the minimum off-time and minimum on-time limits
Input Decoupling Capacitors
of the regulator. The minimum off-time limit imposes a The LTM4625 module should be connected to a low AC maximum duty cycle which can be calculated as: impedance DC source. For the regulator, a 10µF input DMAX = 1 – (tOFF(MIN) • fSW) ceramic capacitor is required for RMS ripple current de- where t coupling. Bulk input capacitance is only needed when the OFF(MIN) is the minimum off-time, typically 70ns for LTM4625, and f input source impedance is compromised by long inductive SW (Hz) is the switching frequency. Conversely the minimum on-time limit imposes a minimum leads, traces or not enough source capacitance. The bulk duty cycle of the converter which can be calculated as: capacitor can be an aluminum electrolytic capacitor or polymer capacitor. DMIN = tON(MIN) • fSW Without considering the inductor ripple current, the RMS where tON(MIN) is the minimum on-time, typically 40ns current of the input capacitor can be estimated as: for LTM4625. In the rare cases where the minimum duty cycle is surpassed, the output voltage will still remain I I OUT(MAX) • D •(1–D) in regulation, but the switching frequency will decrease CIN(RMS) = η% from its programmed value. Note that additional thermal derating may be applied. See the Thermal Considerations where η% is the estimated efficiency of the power module. and Output Current Derating section in this data sheet.
Output Decoupling Capacitors Output Voltage Programming
With an optimized high frequency, high bandwidth design, The PWM controller has an internal 0.6V reference voltage. only a single low ESR output ceramic capacitor is required As shown in the Block Diagram, a 60.4k internal feedback for the LTM4625 to achieve low output ripple voltage and resistor connects the V very good transient response. In extreme cold or hot tem- OUT and FB pins together. Adding a resistor, R perature or high output voltage case, additional ceramic FB, from FB pin to SGND programs the output voltage: capacitor or tantalum-polymer capacitor is required due to variation of actual capacitance over bias voltage and 0.6V R temperature. Table 7 shows a matrix of different output FB = • 60.4k voltages and output capacitors to minimize the voltage VOUT – 0.6V droop and overshoot during a 1A or 2A load-step tran-
Table 1. RFB Resistor Table vs Various Output Voltages
sient. Additional output filtering may be required by the
V
system designer if further reduction of output ripple or
OUT (V) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 5.0
R dynamic transient spikes is required. The Analog Devices FB (kΩ) OPEN 90.9 60.4 40.2 30.1 19.1 13.3 8.25 LTpowerCAD® design tool is available to download online for output ripple, stability and transient response analysis for further optimization. Rev D For more information www.analog.com 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photo Design Resources Related Parts