Datasheet HIP2210, HIP2211 (Renesas) - 8
| Manufacturer | Renesas |
| Description | 100V, 3A Source, 4A Sink, High Frequency Half-Bridge Drivers with Tri-Level PWM Input and Adjustable Dead Time |
| Pages / Page | 28 / 8 — Boldface limits apply across the operating temperature range, -40°C to … |
| File Format / Size | PDF / 608 Kb |
| Document Language | English |
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued). Min. Max. Parameters. Symbol
Model Line for this Datasheet
Text Version of Document
HIP2210, HIP2211 2. Specifications VDD = HB = EN = 12V; VSS = HS = 0V; HI = LI = 0; VREF = 5V; PWM = 2.5V. No load on LO or HO, unless otherwise specified.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) Min Max Parameters Symbol Test Conditions (Note 11) Typ (Note 11) Units HI and LI Inputs (HIP2211)
Low Level Threshold VIL
1.29
1.4
1.47
V High Level Threshold VIH
1.84
2.1
2.35
V Input Threshold Hysteresis VHYS - 0.7 - V Input Pull-Down Resistance RIN HI = LI = VDD; Resistance to VSS - 95 - kΩ Minimum Input Pulse Width for TMIN No load on HO and LO; Output drives - 10 - ns Response at Output to rail
Tri-Level PWM Input (HIP2210)
Middle to High Level Threshold VPWMHR VREF = 2.7V and 5.5V
63.6
66
69.7
% VREF High to Middle Level Threshold VPWMHF VREF = 2.7V and 5.5V
53.7
56
59.6
% VREF High/Middle Level Hysteresis VREF = 2.7V and 5.5V - 10 - % VREF Low to Middle Level Threshold VPWMLR VREF = 2.7V and 5.5V
30.3
33
36.3
% VREF Middle to Low Level Threshold VPWMLF VREF = 2.7V and 5.5V
19.5
23
26.3
% VREF Low/Middle Level Hysteresis VREF = 2.7V and 5.5V - 10 - % VREF PWM Open Circuit Voltage VFLOAT PWM pin floating; VREF = 2.7V and
48
50
52
% VREF 5.5V Logic High Input Current IPWMH PWM = 3V; VREF = 3V; Sourcing - 16 - µA Logic Low Input Current IPWML PWM = 0V; VREF = 3V; Sinking - 16 - µA PWM Pull-Up Resistance RUP To VREF - 180 - kΩ PWM Pull-Down Resistance RDOWN To VSS - 180 - kΩ Minimum Input Pulse Width for TMIN No load on HO and LO; Output drives - 20 - ns Response at Output to rail
VREF Input (HIP2210)
VREF Enabled Rising Threshold VVREF_R PWM = 0; EN = 1; RDT = 1kΩ - 2.55
2.7
V VREF Disabled Hysteresis VVREF_H PWM = 0; EN = 1; RDT = 1kΩ - 0.18 - V VREF Enable Delay tVREF_R PWM = 0; EN = 1; RDT = 1kΩ - 175 - ns VREF Disabled Delay tVREF_F PWM = 0; EN = 1; RDT = 1kΩ - 110 - ns VREF Pull-Down Resistance to RVREF VREF = 3V; PWM = Float - 90 - kΩ VSS
EN Input (HIP2210)
Low-Level Threshold VENL
1.26
1.38
1.47
V High-Level Threshold VENH
1.84
2.1
2.31
V Input Threshold Hysteresis VHYS - 0.72 - V Input Pull-Down Resistance REN VEN = VDD; To VSS - 90 - kΩ EN High Propagation Delay tENH RDT = 1kΩ; PWM = 0
450
800
1100
ns EN Low Propagation Delay tENL RDT = 1kΩ; PWM = 0 - 115
150
ns
Undervoltage Protection
VDD Rising UVLO Threshold VDDR
5.3
5.6
5.9
V VDD Falling UVLO Threshold VDDF
4.75
5.1
5.35
V VDD Threshold Hysteresis VDDH - 0.5 - V FN9347 Rev.1.01 Page 8 of 27 Jun.23.20 Document Outline Related Literature Features Applications Contents 1. Overview 1.1 Block Diagrams 1.2 Ordering Information 1.3 Pin Configurations 1.4 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Information 2.3 Recommended Operating Conditions 2.4 Electrical Specifications 2.5 Switching Specifications 2.6 Timing Diagrams 3. Typical Performance Curves 4. Functional Description 4.1 Gate Drive for NMOS Half-Bridge 4.2 Functional Overview 5. Applications Information 5.1 HI/LI Input Control (HIP2211 Only) 5.2 PWM Input Control (HIP2210 Only) 5.3 VREF Input (HIP2210 Only) 5.4 EN Pin (HIP2210 Only) 5.5 Power Sequencing HIP2210 5.6 Selecting the Boot Capacitor Value 5.7 VDD Decoupling Capacitor 5.8 RDT and Dead Time Delay (HIP2210 Only) 5.9 HO and LO Outputs 5.10 Power Dissipation 5.10.1 Gate Power (for the HO and LO Outputs) 5.10.2 Boot Diode Dissipation 5.10.3 Dynamic Operating Current 5.10.4 Total Power Dissipation 5.10.5 Junction Operating Temperature 6. PCB Layout Guidelines 6.1 PCB Layout and EPAD Recommendation 7. Revision History 8. Package Outline Drawings
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) Min Max Parameters Symbol Test Conditions (Note 11) Typ (Note 11) Units HI and LI Inputs (HIP2211)
Low Level Threshold VIL
1.29
1.4
1.47
V High Level Threshold VIH
1.84
2.1
2.35
V Input Threshold Hysteresis VHYS - 0.7 - V Input Pull-Down Resistance RIN HI = LI = VDD; Resistance to VSS - 95 - kΩ Minimum Input Pulse Width for TMIN No load on HO and LO; Output drives - 10 - ns Response at Output to rail
Tri-Level PWM Input (HIP2210)
Middle to High Level Threshold VPWMHR VREF = 2.7V and 5.5V
63.6
66
69.7
% VREF High to Middle Level Threshold VPWMHF VREF = 2.7V and 5.5V
53.7
56
59.6
% VREF High/Middle Level Hysteresis VREF = 2.7V and 5.5V - 10 - % VREF Low to Middle Level Threshold VPWMLR VREF = 2.7V and 5.5V
30.3
33
36.3
% VREF Middle to Low Level Threshold VPWMLF VREF = 2.7V and 5.5V
19.5
23
26.3
% VREF Low/Middle Level Hysteresis VREF = 2.7V and 5.5V - 10 - % VREF PWM Open Circuit Voltage VFLOAT PWM pin floating; VREF = 2.7V and
48
50
52
% VREF 5.5V Logic High Input Current IPWMH PWM = 3V; VREF = 3V; Sourcing - 16 - µA Logic Low Input Current IPWML PWM = 0V; VREF = 3V; Sinking - 16 - µA PWM Pull-Up Resistance RUP To VREF - 180 - kΩ PWM Pull-Down Resistance RDOWN To VSS - 180 - kΩ Minimum Input Pulse Width for TMIN No load on HO and LO; Output drives - 20 - ns Response at Output to rail
VREF Input (HIP2210)
VREF Enabled Rising Threshold VVREF_R PWM = 0; EN = 1; RDT = 1kΩ - 2.55
2.7
V VREF Disabled Hysteresis VVREF_H PWM = 0; EN = 1; RDT = 1kΩ - 0.18 - V VREF Enable Delay tVREF_R PWM = 0; EN = 1; RDT = 1kΩ - 175 - ns VREF Disabled Delay tVREF_F PWM = 0; EN = 1; RDT = 1kΩ - 110 - ns VREF Pull-Down Resistance to RVREF VREF = 3V; PWM = Float - 90 - kΩ VSS
EN Input (HIP2210)
Low-Level Threshold VENL
1.26
1.38
1.47
V High-Level Threshold VENH
1.84
2.1
2.31
V Input Threshold Hysteresis VHYS - 0.72 - V Input Pull-Down Resistance REN VEN = VDD; To VSS - 90 - kΩ EN High Propagation Delay tENH RDT = 1kΩ; PWM = 0
450
800
1100
ns EN Low Propagation Delay tENL RDT = 1kΩ; PWM = 0 - 115
150
ns
Undervoltage Protection
VDD Rising UVLO Threshold VDDR
5.3
5.6
5.9
V VDD Falling UVLO Threshold VDDF
4.75
5.1
5.35
V VDD Threshold Hysteresis VDDH - 0.5 - V FN9347 Rev.1.01 Page 8 of 27 Jun.23.20 Document Outline Related Literature Features Applications Contents 1. Overview 1.1 Block Diagrams 1.2 Ordering Information 1.3 Pin Configurations 1.4 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Information 2.3 Recommended Operating Conditions 2.4 Electrical Specifications 2.5 Switching Specifications 2.6 Timing Diagrams 3. Typical Performance Curves 4. Functional Description 4.1 Gate Drive for NMOS Half-Bridge 4.2 Functional Overview 5. Applications Information 5.1 HI/LI Input Control (HIP2211 Only) 5.2 PWM Input Control (HIP2210 Only) 5.3 VREF Input (HIP2210 Only) 5.4 EN Pin (HIP2210 Only) 5.5 Power Sequencing HIP2210 5.6 Selecting the Boot Capacitor Value 5.7 VDD Decoupling Capacitor 5.8 RDT and Dead Time Delay (HIP2210 Only) 5.9 HO and LO Outputs 5.10 Power Dissipation 5.10.1 Gate Power (for the HO and LO Outputs) 5.10.2 Boot Diode Dissipation 5.10.3 Dynamic Operating Current 5.10.4 Total Power Dissipation 5.10.5 Junction Operating Temperature 6. PCB Layout Guidelines 6.1 PCB Layout and EPAD Recommendation 7. Revision History 8. Package Outline Drawings
