Datasheet ADL5504 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 450 MHz TO 6000 MHz TruPwr Detector |
| Pages / Page | 24 / 5 — ADL5504. Parameter. Test Conditions. Min. Typ. Max. Unit |
| Revision | A |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
ADL5504. Parameter. Test Conditions. Min. Typ. Max. Unit
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ADL5504 Parameter Test Conditions Min Typ Max Unit
RF INPUT (f = 6000 MHz) Input RFIN to output VRMS Input Impedance No termination 90||0.31 Ω||pF RMS Conversion Dynamic Range1 CW input, −40°C < TA < +85°C ±1 dB Error3 25 dB ±2 dB Error3 34 dB Maximum Input Level ±0.25 dB error3 12 dBm Minimum Input Level ±1 dB error3 −16 dBm Conversion Gain VRMS = (gain × VIN) + intercept 0.82 V/V rms Output Intercept4 -0.005 V Output Voltage, High Input Power PIN = 5 dBm, 400 mV rms 0.314 V Output Voltage, Low Input Power PIN = −15 dBm, 40 mV rms 0.027 V Temperature Sensitivity PIN = 0 dBm 25°C < TA < 85°C 0.0108 dB/°C −40°C < TA < +25°C 0.0120 dB/°C VRMS OUTPUT Pin VRMS Output Offset No signal at RFIN 10 100 mV Maximum Output Voltage VS = 3.0 V, RLOAD ≥ 10 kΩ 2.5 V Available Output Current 3 mA Pulse Response Time 10 dB step, 10% to 90% of settling level, no filter 3 µs capacitor ENABLE INTERFACE Pin ENBL Logic Level to Enable Power, High Condition 2.5 V ≤ VS ≤ 3.3 V, −40°C < TA < +85°C 1.8 VPOS V Input Current when High 2.5 V at ENBL, –40°C < TA < +85°C 0.05 0.1 µA Logic Level to Disable Power, Low Condition 2.5 V ≤ VS ≤ 3.3 V, −40°C < TA < +85°C −0.5 +0.5 V Power-Up Response Time5 CFLTR = open, 0 dBm at RFIN 1 µs CFLTR = 10 nF, 0 dBm at RFIN 8 µs POWER SUPPLIES Operating Range −40°C < TA < +85°C 2.5 3.3 V Quiescent Current6 No signal at RFIN, ENBL high input condition 1.8 mA Disable Current7 ENBL input low condition 0.1 1 µA 1 The available output swing and, therefore, the dynamic range are altered by the supply voltage; see Figure 8. 2 Error referred to delta from 25°C response; see Figure 13 to Figure 15 and Figure 19 to Figure 21. 3 Error referred to best-fit line at 25°C; see Figure 10 to Figure 12 and Figure 16 to Figure 18. 4 Calculated using linear regression. 5 The response time is measured from 10% to 90% of settling level; see Figure 31 to Figure 33. 6 Supply current is input level-dependent; see Figure 27. 7 Guaranteed but not tested; limits are specified at six sigma levels. Rev. A | Page 5 of 24 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Circuit Description RMS Circuit Description and Filtering Filtering Output Buffer Applications Information Basic Connections RF Input Interfacing Resistive Tap RF Input Multiple RF Inputs Linearity Output Swing Output Offset Output Drive Capability and Buffering Selecting the Square-Domain Filter and Output Low-Pass Filter Power Consumption, Enable, and Power-On/Power-Off Response Time Device Calibration and Error Calculation Calibration for Improved Accuracy Drift over a Reduced Temperature Range Device Handling Evaluation Board Land Pattern and Soldering Information Outline Dimensions Ordering Guide
ADL5504 Parameter Test Conditions Min Typ Max Unit
RF INPUT (f = 6000 MHz) Input RFIN to output VRMS Input Impedance No termination 90||0.31 Ω||pF RMS Conversion Dynamic Range1 CW input, −40°C < TA < +85°C ±1 dB Error3 25 dB ±2 dB Error3 34 dB Maximum Input Level ±0.25 dB error3 12 dBm Minimum Input Level ±1 dB error3 −16 dBm Conversion Gain VRMS = (gain × VIN) + intercept 0.82 V/V rms Output Intercept4 -0.005 V Output Voltage, High Input Power PIN = 5 dBm, 400 mV rms 0.314 V Output Voltage, Low Input Power PIN = −15 dBm, 40 mV rms 0.027 V Temperature Sensitivity PIN = 0 dBm 25°C < TA < 85°C 0.0108 dB/°C −40°C < TA < +25°C 0.0120 dB/°C VRMS OUTPUT Pin VRMS Output Offset No signal at RFIN 10 100 mV Maximum Output Voltage VS = 3.0 V, RLOAD ≥ 10 kΩ 2.5 V Available Output Current 3 mA Pulse Response Time 10 dB step, 10% to 90% of settling level, no filter 3 µs capacitor ENABLE INTERFACE Pin ENBL Logic Level to Enable Power, High Condition 2.5 V ≤ VS ≤ 3.3 V, −40°C < TA < +85°C 1.8 VPOS V Input Current when High 2.5 V at ENBL, –40°C < TA < +85°C 0.05 0.1 µA Logic Level to Disable Power, Low Condition 2.5 V ≤ VS ≤ 3.3 V, −40°C < TA < +85°C −0.5 +0.5 V Power-Up Response Time5 CFLTR = open, 0 dBm at RFIN 1 µs CFLTR = 10 nF, 0 dBm at RFIN 8 µs POWER SUPPLIES Operating Range −40°C < TA < +85°C 2.5 3.3 V Quiescent Current6 No signal at RFIN, ENBL high input condition 1.8 mA Disable Current7 ENBL input low condition 0.1 1 µA 1 The available output swing and, therefore, the dynamic range are altered by the supply voltage; see Figure 8. 2 Error referred to delta from 25°C response; see Figure 13 to Figure 15 and Figure 19 to Figure 21. 3 Error referred to best-fit line at 25°C; see Figure 10 to Figure 12 and Figure 16 to Figure 18. 4 Calculated using linear regression. 5 The response time is measured from 10% to 90% of settling level; see Figure 31 to Figure 33. 6 Supply current is input level-dependent; see Figure 27. 7 Guaranteed but not tested; limits are specified at six sigma levels. Rev. A | Page 5 of 24 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Circuit Description RMS Circuit Description and Filtering Filtering Output Buffer Applications Information Basic Connections RF Input Interfacing Resistive Tap RF Input Multiple RF Inputs Linearity Output Swing Output Offset Output Drive Capability and Buffering Selecting the Square-Domain Filter and Output Low-Pass Filter Power Consumption, Enable, and Power-On/Power-Off Response Time Device Calibration and Error Calculation Calibration for Improved Accuracy Drift over a Reduced Temperature Range Device Handling Evaluation Board Land Pattern and Soldering Information Outline Dimensions Ordering Guide
