Datasheet AD8363 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 50 Hz to 6 GHz 50 dB TruPwr Detector |
| Pages / Page | 29 / 8 — AD8363. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. CM T. … |
| Revision | B |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
AD8363. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. CM T. NHII. TCM2/PWDN 1. 12 VTGT. CHPF 2. 11 VREF. VPOS 3. TOP VIEW. 10 VPOS
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AD8363 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 LO CM T IN NHII NC 16 15 14 13 TCM2/PWDN 1 12 VTGT CHPF 2 11 VREF AD8363 VPOS 3 TOP VIEW 10 VPOS COMM 4 9 COMM 5 6 7 8 F P P UT O EM CL V VSET T NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD IS THE SYSTEM COMMON CONNECTION AND IT MUST HAVE BOTH A GOOD
002
THERMAL AND GOOD ELECTRICAL CONNECTION TO GROUND.
07368- Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin Equivalent No. Mnemonic Description Circuit
1 TCM2/PWDN This is a dual function pin used for controlling the amount of nonlinear intercept temperature See Figure 39 compensation at voltages <2.5 V and/or for shutting down the device at voltages >4 V. If the shutdown function is not used, this pin can be connected to the VREF pin through a voltage divider. 2 CHPF Connect this pin to VPOS via a capacitor to determine the −3 dB point of the input signal high- See Figure 48 pass filter. Only add a capacitor when operating at frequencies below 10 MHz. 3, 10 VPOS Supply for the Device. Connect these pins to a 5 V power supply. Pin 3 and Pin 10 are not internally Not connected; therefore, both must connect to the source. applicable 4, 9 COMM System Common Connection. Connect these pins via low impedance to system common. Not applicable 5 CLPF Connection for Loop Filter Integration (Averaging) Capacitor. Connect a ground-referenced See Figure 41 capacitor to this pin. A resistor can be connected in series with this capacitor to improve loop stability and response time. Minimum CLPF value is 390 pF. 6 VOUT Output Pin in Measurement Mode (Error Amplifier Output). In measurement mode, this pin is See Figure 41 connected to VSET. This pin can be used to drive a gain control when the device is used in controller mode. 7 VSET The voltage applied to this pin sets the decibel value of the required RF input voltage that results See Figure 40 in zero current flow in the loop integrating capacitor pin, CLPF. This pin controls the variable gain amplifier (VGA) gain such that a 50 mV change in VSET reduces the gain by approximately 1 dB. 8 TEMP Temperature Sensor Output. See Figure 35 11 VREF General-Purpose Reference Voltage Output of 2.3 V. See Figure 36 12 VTGT The voltage applied to this pin determines the target power at the input of the RF squaring circuit. The See Figure 42 intercept voltage is proportional to the voltage applied to this pin. The use of a lower target voltage increases the crest factor capacity; however, this may affect the system loop response. 13 NC No Connect. Not applicable 14 INHI This is the RF input pin for frequencies up to and including 2.6 GHz. The RF input signal is normally See Figure 34 ac-coupled to this pin through a coupling capacitor. 15 INLO This is the RF input pin for frequencies above 2.6 GHz. The RF input signal is normally ac-coupled See Figure 34 to this pin through a coupling capacitor. 16 TCM1 This pin is used to adjust the intercept temperature compensation. Connect this pin to VREF See Figure 38 through a voltage divider or to an external dc source. EPAD Exposed Pad. The exposed pad is the system common connection and it must have both a good Not thermal and good electrical connection to ground. applicable Rev. B | Page 8 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE CHOICE OF RF INPUT PIN SMALL SIGNAL LOOP RESPONSE TEMPERATURE SENSOR INTERFACE VREF INTERFACE TEMPERATURE COMPENSATION INTERFACE POWER-DOWN INTERFACE VSET INTERFACE OUTPUT INTERFACE VTGT INTERFACE MEASUREMENT MODE BASIC CONNECTIONS SYSTEM CALIBRATION AND ERROR CALCULATION OPERATION TO 125°C OUTPUT VOLTAGE SCALING OFFSET COMPENSATION, MINIMUM CLPF, AND MAXIMUM CHPF CAPACITANCE VALUES CHOOSING A VALUE FOR CLPF RF PULSE RESPONSE AND VTGT CONTROLLER MODE BASIC CONNECTIONS CONSTANT OUTPUT POWER OPERATION DESCRIPTION OF RF CHARACTERIZATION EVALUATION AND CHARACTERIZATION CIRCUIT BOARD LAYOUTS ASSEMBLY DRAWINGS OUTLINE DIMENSIONS ORDERING GUIDE
AD8363 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 LO CM T IN NHII NC 16 15 14 13 TCM2/PWDN 1 12 VTGT CHPF 2 11 VREF AD8363 VPOS 3 TOP VIEW 10 VPOS COMM 4 9 COMM 5 6 7 8 F P P UT O EM CL V VSET T NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD IS THE SYSTEM COMMON CONNECTION AND IT MUST HAVE BOTH A GOOD
002
THERMAL AND GOOD ELECTRICAL CONNECTION TO GROUND.
07368- Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin Equivalent No. Mnemonic Description Circuit
1 TCM2/PWDN This is a dual function pin used for controlling the amount of nonlinear intercept temperature See Figure 39 compensation at voltages <2.5 V and/or for shutting down the device at voltages >4 V. If the shutdown function is not used, this pin can be connected to the VREF pin through a voltage divider. 2 CHPF Connect this pin to VPOS via a capacitor to determine the −3 dB point of the input signal high- See Figure 48 pass filter. Only add a capacitor when operating at frequencies below 10 MHz. 3, 10 VPOS Supply for the Device. Connect these pins to a 5 V power supply. Pin 3 and Pin 10 are not internally Not connected; therefore, both must connect to the source. applicable 4, 9 COMM System Common Connection. Connect these pins via low impedance to system common. Not applicable 5 CLPF Connection for Loop Filter Integration (Averaging) Capacitor. Connect a ground-referenced See Figure 41 capacitor to this pin. A resistor can be connected in series with this capacitor to improve loop stability and response time. Minimum CLPF value is 390 pF. 6 VOUT Output Pin in Measurement Mode (Error Amplifier Output). In measurement mode, this pin is See Figure 41 connected to VSET. This pin can be used to drive a gain control when the device is used in controller mode. 7 VSET The voltage applied to this pin sets the decibel value of the required RF input voltage that results See Figure 40 in zero current flow in the loop integrating capacitor pin, CLPF. This pin controls the variable gain amplifier (VGA) gain such that a 50 mV change in VSET reduces the gain by approximately 1 dB. 8 TEMP Temperature Sensor Output. See Figure 35 11 VREF General-Purpose Reference Voltage Output of 2.3 V. See Figure 36 12 VTGT The voltage applied to this pin determines the target power at the input of the RF squaring circuit. The See Figure 42 intercept voltage is proportional to the voltage applied to this pin. The use of a lower target voltage increases the crest factor capacity; however, this may affect the system loop response. 13 NC No Connect. Not applicable 14 INHI This is the RF input pin for frequencies up to and including 2.6 GHz. The RF input signal is normally See Figure 34 ac-coupled to this pin through a coupling capacitor. 15 INLO This is the RF input pin for frequencies above 2.6 GHz. The RF input signal is normally ac-coupled See Figure 34 to this pin through a coupling capacitor. 16 TCM1 This pin is used to adjust the intercept temperature compensation. Connect this pin to VREF See Figure 38 through a voltage divider or to an external dc source. EPAD Exposed Pad. The exposed pad is the system common connection and it must have both a good Not thermal and good electrical connection to ground. applicable Rev. B | Page 8 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE CHOICE OF RF INPUT PIN SMALL SIGNAL LOOP RESPONSE TEMPERATURE SENSOR INTERFACE VREF INTERFACE TEMPERATURE COMPENSATION INTERFACE POWER-DOWN INTERFACE VSET INTERFACE OUTPUT INTERFACE VTGT INTERFACE MEASUREMENT MODE BASIC CONNECTIONS SYSTEM CALIBRATION AND ERROR CALCULATION OPERATION TO 125°C OUTPUT VOLTAGE SCALING OFFSET COMPENSATION, MINIMUM CLPF, AND MAXIMUM CHPF CAPACITANCE VALUES CHOOSING A VALUE FOR CLPF RF PULSE RESPONSE AND VTGT CONTROLLER MODE BASIC CONNECTIONS CONSTANT OUTPUT POWER OPERATION DESCRIPTION OF RF CHARACTERIZATION EVALUATION AND CHARACTERIZATION CIRCUIT BOARD LAYOUTS ASSEMBLY DRAWINGS OUTLINE DIMENSIONS ORDERING GUIDE
