Datasheet AD8364 (Analog Devices) - 6

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AD8364 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
SETPOINT INPUT Pin VSTA and VSTB Voltage Range Law conformance error ≤1 dB 0.5 3.75 V Input Resistance 68 kΩ Logarithmic Scale Factor f = 450 MHz, −40°C ≤ TA ≤ +85°C 50 mV/dB Logarithmic Intercept f = 450 MHz, −40°C ≤ TA ≤ +85°C, referred to 50 Ω −55 dBm CHANNEL DIFFERENCE OUTPUT Pin OUTP and OUTN Voltage Range Min RL ≥ 200 Ω to ground 0.1 V Voltage Range Max RL ≥ 200 Ω to ground VS − 0.15 V Source/Sink Current OUTP and OUTN held at VS/2, to 1% change 70 mA DIFFERENCE LEVEL ADJUST Pin VLVL Voltage Range3 OUT[P, N] = FBK[A, B] 0 5 V OUT[P,N] Voltage Range OUT[P, N] = FBK[A, B] 0 VS − V 0.15 Input Resistance 1 kΩ TEMPERATURE COMPENSATION Pin ADJA and ADJB Input Voltage Range 0 2.5 V Input Resistance >1 MΩ VOLTAGE REFERENCE Pin VREF Output Voltage RF in = −55 dBm 2.5 V Temperature Sensitivity −40°C ≤ TA ≤ +85°C 0.4 mV/°C Current Limit Source/Sink 1% change 10/3 mA TEMPERATURE REFERENCE Pin TEMP Output Voltage TA = 25°C, RL ≥ 10 kΩ 0.62 V Temperature Coefficient −40°C ≤ TA ≤ +85°C, RL ≥ 10 kΩ 2 mV/°C Current Source/Sink TA = 25°C to 1% change 1.6/2 mA POWER-DOWN INTERFACE Pin PWDN Logic Level to Enable Logic LO enables 1 V Logic Level to Disable Logic HI disables 3 V Input Current Logic HI PWDN = 5 V 95 µA Logic LO PWDN = 0 V <100 µA Enable Time PWDN LO to OUTA/OUTB at 100% final value, 2 µs CLPA/B = Open, CHPA/B = 10 nF, RF in = 0 dBm Disable Time PWDN HI to OUTA/OUTB at 10% final value, 1.6 µs CLPA/B = Open, CHPA/B = 10nF, RF in = 0 dBm POWER INTERFACE Pin VPS[A, B], VPSR Supply Voltage 4.5 5.5 V Quiescent Current RF in = −55 dBm, VS = 5 V 70 mA −40°C ≤ TA ≤ +85°C 90 mA Supply Current PWDN enabled, VS = 5 V 500 µA −40°C ≤ TA ≤ +85°C 900 µA 1 Best fit line, linear regression. 2 See Figure 73 for a plot of isolation vs. frequency for a ±1 dB error. 3 VLVL + OUTA/2 should not exceed VPSA − 1.31 V. Likewise, VLVL + OUTB/2 should not exceed VPSB − 1.31 V. Rev. C | Page 6 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE OFFSET COMPENSATION TEMPERATURE SENSOR INTERFACE VREF INTERFACE POWER-DOWN INTERFACE VST[A, B] INTERFACE OUT[A, B, P, N] OUTPUTS MEASUREMENT CHANNEL DIFFERENCE OUTPUT USING OUT[P, N] CONTROLLER MODE RF MEASUREMENT MODE BASIC CONNECTIONS CONTROLLER MODE BASIC CONNECTIONS Automatic Power Control Automatic Gain Control CONSTANT OUTPUT POWER OPERATION GAIN-STABLE TRANSMITTER/RECEIVER TEMPERATURE COMPENSATION ADJUSTMENT DEVICE CALIBRATION AND ERROR CALCULATION SELECTING CALIBRATION POINTS TO IMPROVE ACCURACY OVER A REDUCED RANGE CHANNEL ISOLATION ALTERING THE SLOPE CHOOSING THE RIGHT VALUE FOR CHP[A, B] AND CLP[A, B] RF BURST RESPONSE TIME SINGLE-ENDED INPUT OPERATION PRINTED CIRCUIT BOARD CONSIDERATIONS PACKAGE CONSIDERATIONS DESCRIPTION OF CHARACTERIZATION BASIS FOR ERROR CALCULATIONS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE