Datasheet ADRV9026 (Analog Devices)

Integrated, Quad RF Transceiver with Observation Path Data Sheet ADRV9026 FEATURES
The complete transceiver subsystem includes automatic and
4 differential transmitters
manual attenuation control, dc offset correction, quadrature error
4 differential receivers
correction (QEC), and digital filtering, eliminating the need for
2 observation receivers with 2 inputs each
these functions in the digital baseband. Other auxiliary functions
Center frequency: 650 MHz to 6000 MHz
such as analog-to-digital converters (ADCs), digital-to-analog
Maximum receiver bandwidth: 200 MHz
converters (DACs), and general-purpose input/outputs
Maximum transmitter large signal bandwidth: 200 MHz
(GPIOs) that provide an array of digital control options are also
Maximum transmitter synthesis bandwidth: 450 MHz
integrated.
Maximum observation receiver bandwidth: 450 MHz
To achieve a high level of RF performance, the transceiver
Fully integrated independent fractional-N radio frequency
includes five fully integrated phase-locked loops (PLLs). Two
synthesizers
PLLs provide low noise and low power fractional-N RF
Fully integrated clock synthesizer
synthesis for the transmitter and receiver signal paths. A third
Multichip phase synchronization for all local oscillators and
fully integrated PLL supports an independent local oscillator (LO)
baseband clocks
mode for the observation receiver. The fourth PLL generates
Support for TDD and FDD applications
the clocks needed for the converters and digital circuits, and a
12.288 Gbps JESD204B/JESD204C digital interface
fifth PLL provides the clock for the serial data interface.
APPLICATIONS
A multichip synchronization mechanism synchronizes the
3G/4G/5G TDD and FDD massive MIMO, macro and small cell
phase of all LOs and baseband clocks between multiple
base stations
ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the
GENERAL DESCRIPTION
digital control interface. The ADRV9026 is a highly integrated, radio frequency (RF) agile The serial data interface consists of four serializer lanes and four transceiver offering four independently control ed transmitters, deserializer lanes. The interface supports both the JESD204B and dedicated observation receiver inputs for monitoring each JESD204C standards, operating at data rates up to 12.288 Gbps. transmitter channel, four independently control ed receivers, The interface also supports interleaved mode for lower integrated synthesizers, and digital signal processing functions bandwidths, thus reducing the number of high speed data providing a complete transceiver solution. The device provides interface lanes to one. Both fixed and floating-point data the performance demanded by cel ular infrastructure applications, formats are supported. The floating-point format al ows such as small cell base station radios, macro 3G/4G/5G systems, internal automatic gain control (AGC) to be invisible to the and massive multiple in/multiple out (MIMO) base stations. demodulator device. The receiver subsystem consists of four independent, wide The ADRV9026 is powered directly from 1.0 V, 1.3 V, and bandwidth, direct conversion receivers with wide dynamic 1.8 V regulators and is control ed via a standard serial range. The four independent transmitters use a direct conversion peripheral interface (SPI) serial port. Comprehensive power- modulator resulting in low noise operation with low power down modes are included to minimize power consumption in consumption. The device also includes two wide bandwidth, normal use. The ADRV9026 is packaged in a 14 mm × 14 mm, time shared, observation path receivers with two inputs each for 289-ball chip scale ball grid array (CSP_BGA). monitoring transmitter outputs.
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Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Transmitters and Receivers Synthesizers, Auxiliary Converters, and Clock References Digital Specifications Power Supply Specifications Current Consumption TDD Operation—Four Receiver Channels Enabled TDD Operation—Four Transmitter and One Observation Receiver Channels Enabled FDD Operation—LO1 and LO2, Four Receiver, Four Transmitter, and One Observation Receiver Channels Enabled Digital Interface and Timing Specifications Absolute Maximum Ratings Junction Temperature Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Band 1800 MHz Band 2600 MHz Band 3800 MHz Band 4800 MHz Band 5700 MHz Band Theory of Operation General Transmitter Receiver Observation Receiver Clock Input Synthesizers RF Synthesizers Auxiliary Synthesizer Clock Synthesizer SPI Interface GPIO_x Pins Auxiliary Converters GPIO_ANA_x/AUXDAC_x AUXADC_x JTAG Boundary Scan Applications Information Power Supply Sequence Data Interface Outline Dimensions Ordering Guide