Datasheet AD9361 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | RF Agile Transceiver |
| Pages / Page | 36 / 3 — Data Sheet. AD9361. SPECIFICATIONS. Table 1. Test Conditions/. … |
| Revision | F |
| File Format / Size | PDF / 648 Kb |
| Document Language | English |
Data Sheet. AD9361. SPECIFICATIONS. Table 1. Test Conditions/. Parameter1. Symbol Min. Typ. Max. Unit. Comments
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Data Sheet AD9361 SPECIFICATIONS
Electrical characteristics at VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, and al other VDDx pins = 1.3 V, TA = 25°C, unless otherwise noted.
Table 1. Test Conditions/ Parameter1 Symbol Min Typ Max Unit Comments
RECEIVERS, GENERAL Center Frequency 70 6000 MHz Gain Minimum 0 dB Maximum 74.5 dB At 800 MHz 73.0 dB At 2300 MHz (RX1A, RX2A) 72.0 dB At 2300 MHz (RX1B, RX1C, RX2B, RX2C) 65.5 dB At 5500 MHz (RX1A, RX2A) Gain Step 1 dB Received Signal Strength RSSI Indicator Range 100 dB Accuracy ±2 dB RECEIVERS, 800 MHz Noise Figure NF 2 dB Maximum RX gain Third-Order Input Intermodulation IIP3 −18 dBm Maximum RX gain Intercept Point Second-Order Input IIP2 40 dBm Maximum RX gain Intermodulation Intercept Point Local Oscillator (LO) Leakage −122 dBm At RX front-end input Quadrature Gain Error 0.2 % Phase Error 0.2 Degrees Modulation Accuracy (EVM) −42 dB 19.2 MHz reference clock Input S11 −10 dB RX1 to RX2 Isolation RX1A to RX2A, RX1C to RX2C 70 dB RX1B to RX2B 55 dB RX2 to RX1 Isolation RX2A to RX1A, RX2C to RX1C 70 dB RX2B to RX1B 55 dB RECEIVERS, 2.4 GHz Noise Figure NF 3 dB Maximum RX gain Third-Order Input Intermodulation IIP3 −14 dBm Maximum RX gain Intercept Point Second-Order Input IIP2 45 dBm Maximum RX gain Intermodulation Intercept Point LO Leakage −110 dBm At receiver front-end input Quadrature Gain Error 0.2 % Phase Error 0.2 Degrees Modulation Accuracy (EVM) −42 dB 40 MHz reference clock Input S11 −10 dB RX1 to RX2 Isolation RX1A to RX2A, RX1C to RX2C 65 dB RX1B to RX2B 50 dB RX2 to RX1 Isolation RX2A to RX1A, RX2C to RX1C 65 dB RX2B to RX1B 50 dB Rev. F | Page 3 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD9361 SPECIFICATIONS
Electrical characteristics at VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, and al other VDDx pins = 1.3 V, TA = 25°C, unless otherwise noted.
Table 1. Test Conditions/ Parameter1 Symbol Min Typ Max Unit Comments
RECEIVERS, GENERAL Center Frequency 70 6000 MHz Gain Minimum 0 dB Maximum 74.5 dB At 800 MHz 73.0 dB At 2300 MHz (RX1A, RX2A) 72.0 dB At 2300 MHz (RX1B, RX1C, RX2B, RX2C) 65.5 dB At 5500 MHz (RX1A, RX2A) Gain Step 1 dB Received Signal Strength RSSI Indicator Range 100 dB Accuracy ±2 dB RECEIVERS, 800 MHz Noise Figure NF 2 dB Maximum RX gain Third-Order Input Intermodulation IIP3 −18 dBm Maximum RX gain Intercept Point Second-Order Input IIP2 40 dBm Maximum RX gain Intermodulation Intercept Point Local Oscillator (LO) Leakage −122 dBm At RX front-end input Quadrature Gain Error 0.2 % Phase Error 0.2 Degrees Modulation Accuracy (EVM) −42 dB 19.2 MHz reference clock Input S11 −10 dB RX1 to RX2 Isolation RX1A to RX2A, RX1C to RX2C 70 dB RX1B to RX2B 55 dB RX2 to RX1 Isolation RX2A to RX1A, RX2C to RX1C 70 dB RX2B to RX1B 55 dB RECEIVERS, 2.4 GHz Noise Figure NF 3 dB Maximum RX gain Third-Order Input Intermodulation IIP3 −14 dBm Maximum RX gain Intercept Point Second-Order Input IIP2 45 dBm Maximum RX gain Intermodulation Intercept Point LO Leakage −110 dBm At receiver front-end input Quadrature Gain Error 0.2 % Phase Error 0.2 Degrees Modulation Accuracy (EVM) −42 dB 40 MHz reference clock Input S11 −10 dB RX1 to RX2 Isolation RX1A to RX2A, RX1C to RX2C 65 dB RX1B to RX2B 50 dB RX2 to RX1 Isolation RX2A to RX1A, RX2C to RX1C 65 dB RX2B to RX1B 50 dB Rev. F | Page 3 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
