Datasheet AD9361 (Analog Devices) - 6

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AD9361 Data Sheet Test Conditions/ Parameter1 Symbol Min Typ Max Unit Comments
Logic Outputs Output Voltage High 1375 mV Low 1025 mV Output Differential Voltage 150 mV Programmable in 75 mV steps Output Offset Voltage 1200 mV GENERAL-PURPOSE OUTPUTS Output Voltage High VDD_GPO × 0.8 V Low VDD_GPO × 0.2 V Output Current 10 mA SPI TIMING VDD_INTERFACE = 1.8 V SPI_CLK Period tCP 20 ns Pulse Width tMP 9 ns SPI_ENB Setup to First SPI_CLK tSC 1 ns Rising Edge Last SPI_CLK Fal ing Edge to tHC 0 ns SPI_ENB Hold SPI_DI Data Input Setup to SPI_CLK tS 2 ns Data Input Hold to SPI_CLK tH 1 ns SPI_CLK Rising Edge to Output Data Delay 4-Wire Mode tCO 3 8 ns 3-Wire Mode tCO 3 8 ns Bus Turnaround Time, Read tHZM tH tCO (max) ns After BBP drives the last address bit Bus Turnaround Time, Read tHZS 0 tCO (max) ns After AD9361 drives the last data bit DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 1.8 V DATA_CLK Clock Period tCP 16.276 ns 61.44 MHz DATA_CLK and FB_CLK Pulse tMP 45% of tCP 55% of tCP ns Width TX Data TX_FRAME, P0_D, and P1_D Setup to FB_CLK tSTX 1 ns Hold to FB_CLK tHTX 0 ns DATA_CLK to Data Bus Output tDDRX 0 1.5 ns Delay DATA_CLK to RX_FRAME Delay tDDDV 0 1.0 ns Pulse Width ENABLE tENPW tCP ns TXNRX tTXNRXPW tCP ns FDD independent ENSM mode TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode Bus Turnaround Time Before RX tRPRE 2 × tCP ns TDD mode After RX tRPST 2 × tCP ns TDD mode Capacitive Load 3 pF Capacitive Input 3 pF Rev. F | Page 6 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE