Datasheet ADN8834 (Analog Devices) - 3

Data Sheet ADN8834 SPECIFICATIONS
VIN = 2.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY Driver Supply Voltage V 2.7 5.5 V PVIN Controller Supply Voltage V 2.7 5.5 V VDD Supply Current I PWM not switching 3.3 5 mA VDD Shutdown Current I EN/SY = AGND or VLIM/SD = AGND 350 700 µA SD Undervoltage Lockout (UVLO) V V rising 2.45 2.55 2.65 V UVLO VDD UVLO Hysteresis UVLO 80 90 100 mV HYST REFERENCE VOLTAGE V I = 0 mA to 10 mA 2.475 2.50 2.525 V VREF VREF LINEAR OUTPUT Output Voltage V I = 0 A LDR LDR Low 0 V High V V PVIN Maximum Source Current I T = −40°C to +105°C 1.5 A LDR_SOURCE J T = −40°C to +125°C 1.2 A J Maximum Sink Current I T = −40°C to +105°C 1.5 A LDR_SINK J T = −40°C to +125°C 1.2 A J On Resistance I = 0.6 A LDR P-MOSFET R WLCSP, V = 5.0 V 35 50 mΩ DS_PL(ON) PVIN WLCSP, V = 3.3 V 44 60 mΩ PVIN LFCSP, V = 5.0 V 50 65 mΩ PVIN LFCSP, V = 3.3 V 55 75 mΩ PVIN N-MOSFET R WLCSP, V = 5.0 V 31 50 mΩ DS_NL(ON) PVIN WLCSP, V = 3.3 V 40 55 mΩ PVIN LFCSP, V = 5.0 V 45 70 mΩ PVIN LFCSP, V = 3.3 V 50 80 mΩ PVIN Leakage Current P-MOSFET I 0.1 10 µA LDR_P_LKG N-MOSFET I 0.1 10 µA LDR_N_LKG Linear Amplifier Gain A 40 V/V LDR LDR Short-Circuit Threshold I LDR short to PGNDL, enter hiccup 2.2 A LDR_SH_GNDL I LDR short to PVIN, enter hiccup −2.2 A LDR_SH_PVIN(L) Hiccup Cycle T 15 ms HICCUP PWM OUTPUT Output Voltage V I = 0 A V SFB SFB Low 0.06 × V V PVIN High 0.93 × V V PVIN Maximum Source Current I T = −40°C to +105°C 1.5 A SW_SOURCE J T = −40°C to +125°C 1.2 A J Maximum Sink Current I T = −40°C to +105°C 1.5 A SW_SINK J T = −40°C to +125°C 1.2 A J On Resistance I = 0.6 A SW P-MOSFET R WLCSP, V = 5.0 V 47 65 mΩ DS_PS(ON) PVIN WLCSP, V = 3.3 V 60 80 mΩ PVIN LFCSP, V = 5.0 V 60 80 mΩ PVIN LFCSP, V = 3.3 V 70 95 mΩ PVIN Rev. B | Page 3 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Detailed Functional Block Diagram Theory of Operation Analog PID Control Digital PID Control Powering the Controller Enable and Shutdown Oscillator Clock Frequency External Clock Operation Connecting Multiple ADN8834 Devices Temperature Lock Indicator (LFCSP Only) Soft Start on Power-Up TEC Voltage/Current Monitor Voltage Monitor Current Monitor Maximum TEC Voltage Limit Using a Resistor Divider to Set the TEC Voltage Limit Maximum TEC Current Limit Using a Resistor Divider to Set the TEC Current Limit Applications Information Signal Flow Thermistor Setup Thermistor Amplifier (Chopper 1) PID Compensation Amplifier (Chopper 2) MOSFET Driver Amplifiers PWM Output Filter Requirements Inductor Selection Capacitor Selection Input Capacitor Selection Power Dissipation PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB Layout Guidelines Block Diagrams and Signal Flow Guidelines for Reducing Noise and Minimizing Power Loss General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components Example PCB Layout Using Two Layers Outline Dimensions Ordering Guide