Datasheet DS28E18 (Maxim) - 52

DS28E18 1-Wire® to I2C/SPI Bridge with Command Sequencer
SPI Write/Read Bit(s) Command Table 55. SPI Write/Read Bit Command SPI WRITE/READ BIT COMMAND
Sequencer Command B0h Write and/or Read from 1 to 64 bits on the SPI bus. This command enables SPI support for data Typical Usage and addressing in sizes other than 8 bits. For standard 8-bit communication, the SPI Write/Read Byte command is more efficient since this command is limited to 134kHz (max). Write and Read or just Write or Read bits from a length of 1 to 64 bits. SPI Features This command enables support for SPI data/address lengths not 8 bits in width. No 1-Wire commands or 1-Wire data are accepted during execution of the sequence (i.e., during Restriction the execution of the formed packets in the SRAM) and SS must be active to select the SPI slave. SPU must be active to select 1-Wire.
Formed 1-Wire Packet
Command Write Length Read Length Write Bit Array Read Bit Array B0h
Write Length
n: The number of data bits to write from 1 to 64. If this field is set to 0, the Write GAP is skipped, and the write data array should not be transmitted from the host.
Read Length
m: Set to the number of bits to read from 1 to 64. If this field is set to 0, the Read GAP is skipped, and no Read Bit Array should be included in the packet from the host.
Write Bit Array: WBIT[n ]
WBIT[n]: Send the user-defined write data from 1 to 64 bits on byte boundaries. Only the specified number of bits are transmitted.
Read Bit Array: RBIT[m ]
RBIT[m]: An array used to store the bits for the Read operation. This array must be sized on byte boundaries from 1 byte to 8 bytes in size. If the Read Length is 0, the Read Bit Array should not be used. The Read Bit Array must be initialized to FFh. 19-100832 www.maximintegrated.com Maxim Integrated | 52 Document Outline General Description Applications Benefits and Features Simplified Application Block Diagram Absolute Maximum Ratings Package Information 8 TDFN-EP Electrical Characteristics Electrical Characteristics (continued) Typical Operating Characteristics Pin Configuration DS28E18 Pin Description Functional Diagram Block Diagram Detailed Description 64-Bit ROM ID Power-Up ROM ID Serialization 1-Wire Bus System Hardware Configuration Transaction Sequence Initialization 1-Wire ROM Function Commands Search ROM [F0h] Read ROM [33h] Match ROM [55h] Skip ROM [CCh] Resume [A5h] Overdrive-Skip ROM [3Ch] Overdrive-Match ROM [69h] 1-Wire Signaling and Timing Read/Write Time Slots Master-to-Slave Slave-to-Master Improved Network Behavior Device Function Commands Command Start (66h) Write Sequencer Command (11h) Read Sequencer Command (22h) Run Sequencer Command (33h) Device Configuration and Status Commands Write Configuration Command (55h) Read Configuration Command (6Ah) Write GPIO Configuration (83h) Read GPIO Configuration (7Ch) Device Status Command (7Ah) Sequencer Commands I2C Sequencer Interface Commands I2C Start Command I2C Stop Command I2C Write Data Command I2C Read Data Command I2C Read Data with NACK End Command SPI Sequencer Commands SPI Write/Read Byte(s) Command SPI Write/Read Bit(s) Command SS_HIGH Command SS_LOW Command Sequencer Utility Commands GPIO_CTRL Write Command GPIO_CTRL Read Command GPIO_BUF Write Command GPIO_BUF Read Command Delay Command SENS_VDD On Command SENS_VDD Off Command I2C Overview I2C Definitions Bus Idle or Not Busy START Condition STOP Condition Repeated START Condition Data Valid SPI Overview SPI Timing SPI Timing Diagram Power-Up of GPIO/I2C Pins Timeout Typical Application Circuits DS28E18 Configured as an I2C Master Typical Application Circuits (continued) DS28E18 Configured as an SPI Master Ordering Information Revision History