Datasheet AD8468 (Analog Devices) - 7

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Data Sheet AD8468 APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING VLOGIC
The AD8468 comparator is a high speed device. Despite the low noise output stage, it is essential to use proper high
A1 Q1
speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or
+IN OUTPUT
undesired hysteresis. Of critical importance is the use of low
AV –IN
impedance supply planes, particularly the output supply plane (VCC) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the
A2 Q2
lowest inductance return path for switching currents ensures the best possible performance in the target application. 09 -0
GAIN STAGE OUTPUT STAGE
853 08 It is also important to adequately bypass the input and output Figure 9. Simplified Schematic Diagram of the supplies. A 0.1 μF bypass capacitor should be placed as close as TTL-/CMOS-Compatible Output Stage possible to the VCC supply pin. The capacitor should be connected
OPTIMIZING PERFORMANCE
to the GND plane with redundant vias placed to provide a physically short return path for output currents flowing back As with any high speed comparator, proper design and layout from ground to the V techniques are essential for obtaining the specified performance. CC pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Stray capacitance, inductance, common power and ground Parasitic layout inductance should also be strictly controlled to impedances, or other layout issues can severely limit performance maximize the effectiveness of the bypass at high frequencies. and can often cause oscillation. The source impedance should be minimized as much as is practicable. High source impedance,
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
in combination with the parasitic input capacitance of the Specified propagation delay performance can be achieved only comparator, causes an undesirable degradation in bandwidth at by keeping the capacitive load at or below the specified minimums. the input, thus degrading the overall response. Higher impedances The output of the AD8468 is designed to directly drive one encourage undesired coupling. Schottky TTL, three low power Schottky TTL loads, or the
COMPARATOR PROPAGATION
equivalent. For large fanouts, buses, or transmission lines, use
DELAY DISPERSION
an appropriate buffer to maintain the excellent speed and stability of the comparator. The AD8468 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 10 mV to With the rated 15 pF load capacitance applied, more than half VCC – 1 V. Propagation delay dispersion is the variation in of the total device propagation delay is output stage slew time. propagation delay that results from a change in the degree of Because of this, the total propagation delay decreases as VCC overdrive or slew rate (how far or how fast the input signal decreases, and instability in the power supply may appear as exceeds the switching threshold). See Figure 10 and Figure 11. excess delay dispersion. Propagation delay dispersion is a specification that becomes Delay is measured to the 50% point for whatever supply is in important in high speed, time-critical applications, such as data use; thus, the fastest times are observed with the VCC supply at communication, automatic test and measurement, and instru- 2.5 V, and larger values are observed when driving loads that mentation. It is also important in event-driven applications, such switch at other levels. as pulse spectroscopy, nuclear instrumentation, and medical imaging. Overdrive and input slew rate dispersions are not significantly affected by output loading and VCC variations. The AD8468 overdrive dispersion is typically <12 ns as the overdrive varies from 10 mV to 125 mV. This specification The TTL-/CMOS-compatible output stage is shown in the applies to both positive and negative signals because the device simplified schematic diagram (see Figure 9). Because of its has very closely matched delays for both positive-going and inherent symmetry and generally good behavior, this output negative-going inputs and very low output skews. Remember to stage is readily adaptable for driving various filters and other add the actual device offset to the overdrive for repeatable unusual loads. dispersion measurements. Rev. A | Page 7 of 12 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING TTL-/CMOS-COMPATIBLE OUTPUT STAGE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATIONDELAY DISPERSION CROSSOVER BIAS POINT MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS