Datasheet HMC675LP3E (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 10 GHz Latched Comparator with RSCML Output Stage |
| Pages / Page | 10 / 7 — HMC675LP3E. 10 GHz LATCHED COMPARATOR. WITH RSCML OUTPUT STAGE. Pin … |
| File Format / Size | PDF / 556 Kb |
| Document Language | English |
HMC675LP3E. 10 GHz LATCHED COMPARATOR. WITH RSCML OUTPUT STAGE. Pin Descriptions
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HMC675LP3E
v02.0312
10 GHz LATCHED COMPARATOR WITH RSCML OUTPUT STAGE Pin Descriptions
T Pin Number Function Description Interface Schematic M 1 VTP Termination resistor return pin for Vp Input. 2 INP Non-Inverting analog input 3 INN Inverting analog input S - S 4 VTN Termination resistor return pin for Vn input R O 5, 16 Vcci Positive supply voltage input stage. AT Latch enable bar input pin, inverting side. R 6 LE Refer to the Operational Description for more details. A P Latch enable input pin, non-inverting side. 7 LE Refer to the Operational Description for more details. OM C Pin is not connected inside the package. 8 N/C Connect package pin to GND for improved noise. 9, 12 Vcco Positive supply voltage for the output stage. Inverting output. Q bar is at logic low if the analog voltage at the non-inverting input, INP, is greater than the analog 10 Q voltage at the inverting input, INN, provided that the comparator is in compare mode. Refer to the Operational Description for more details. Non-inverting output. Q is at logic high if the analog voltage at the non-inverting input, INP, is greater than the analog 11 Q voltage at the inverting input, INN, provided that the comparator is in compare mode. Refer to the Operational Description for more details. Hysteresis Control pin. This pin should be left disconnected for zero hysteresis. Connect to Vee with a resistor to add 14 HYS the desired amount of hysteresis. Refer to hysteresis graph to determine the correct sizing of Rhys hysteresis control resistor. 13 Vee Negative power supply, -3 V. 15 RTN Return for ESD protection. Package Base Exposed paddle must be connected to Vee. I F nf o or r p mati r o in cfe ur , d nish e e l d iv b e y r A y a nalo n g d t Devi o p ces i la s c bele o ieve rd d t e o rbs e : H acc iutrtatite e M and ic reli rao bl w e. a H v o e C wever o , nrp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No rd Phoe n r O e: 7 n- 81-li 3 n 2 e a 9-4 t w 70 ww 0 • O . rdh e itt r o it nle i . n co e a m
7
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. t www.analog.com Application Support: Phon Trademarks and registered trademarks are the property of their respective owners. e: 978-250-334 A 3 p o plic ra a tio pp n S s u @ p h por ittti : Pte ho.c n om e: 1-800-ANALOG-D
v02.0312
10 GHz LATCHED COMPARATOR WITH RSCML OUTPUT STAGE Pin Descriptions
T Pin Number Function Description Interface Schematic M 1 VTP Termination resistor return pin for Vp Input. 2 INP Non-Inverting analog input 3 INN Inverting analog input S - S 4 VTN Termination resistor return pin for Vn input R O 5, 16 Vcci Positive supply voltage input stage. AT Latch enable bar input pin, inverting side. R 6 LE Refer to the Operational Description for more details. A P Latch enable input pin, non-inverting side. 7 LE Refer to the Operational Description for more details. OM C Pin is not connected inside the package. 8 N/C Connect package pin to GND for improved noise. 9, 12 Vcco Positive supply voltage for the output stage. Inverting output. Q bar is at logic low if the analog voltage at the non-inverting input, INP, is greater than the analog 10 Q voltage at the inverting input, INN, provided that the comparator is in compare mode. Refer to the Operational Description for more details. Non-inverting output. Q is at logic high if the analog voltage at the non-inverting input, INP, is greater than the analog 11 Q voltage at the inverting input, INN, provided that the comparator is in compare mode. Refer to the Operational Description for more details. Hysteresis Control pin. This pin should be left disconnected for zero hysteresis. Connect to Vee with a resistor to add 14 HYS the desired amount of hysteresis. Refer to hysteresis graph to determine the correct sizing of Rhys hysteresis control resistor. 13 Vee Negative power supply, -3 V. 15 RTN Return for ESD protection. Package Base Exposed paddle must be connected to Vee. I F nf o or r p mati r o in cfe ur , d nish e e l d iv b e y r A y a nalo n g d t Devi o p ces i la s c bele o ieve rd d t e o rbs e : H acc iutrtatite e M and ic reli rao bl w e. a H v o e C wever o , nrp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No rd Phoe n r O e: 7 n- 81-li 3 n 2 e a 9-4 t w 70 ww 0 • O . rdh e itt r o it nle i . n co e a m
7
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. t www.analog.com Application Support: Phon Trademarks and registered trademarks are the property of their respective owners. e: 978-250-334 A 3 p o plic ra a tio pp n S s u @ p h por ittti : Pte ho.c n om e: 1-800-ANALOG-D
