Datasheet ADCMP565 (Analog Devices) - 10

link to page 10 link to page 10 link to page 11 link to page 11 link to page 10 ADCMP565 as the variation in propagation delay as the input overdrive
–VH +VH
conditions are changed (Figure 4). For the ADCMP565,
2 2 0V
overdrive dispersion is typically 50 ps as the overdrive is
INPUT
changed from 100 mV to 1 V. This specification applies for
1
both positive and negative overdrive since the ADCMP565 has equal delays for positive and negative going inputs. The 50 ps propagation delay dispersion of the ADCMP565 offers considerable improvement of the 100 ps dispersion of other similar series comparators.
0 1.5V OVERDRIVE INPUT VOLTAGE OUTPUT 20mV OVERDRIVE
02820-0-005
VREF ± VOS
Figure 5. Comparator Hysteresis Transfer Function
DISPERSION 60 Q OUTPUT 50
02820-0-004 Figure 4. Propagation Delay Dispersion
V) 40 m COMPARATOR HYSTERESIS ESIS ( 30
The addition of hysteresis to a comparator is often useful in a
YSTER
noisy environment or where it is not desirable for the com-
H 20
parator to toggle between states when the input signal is at the switching threshold. The transfer function for a comparator
10
with hysteresis is shown in Figure 5. If the input voltage approaches the threshold from the negative direction, the
0–20 –15 –10 –5 0 5 10 15 20
comparator will switch from a 0 to a 1 when the input crosses ∆
LATCH = LE – LEB (mV)
+VH/2. The new switching threshold becomes −VH/2. The 02820-0-006 comparator will remain in a 1 state until the threshold −VH/2 is Figure 6. Comparator Hysteresis Transfer Function crossed coming from the positive direction. In this manner, Using Latch Enable Input noise centered on 0 V input will not cause the comparator to switch states unless it exceeds the region bounded by ±VH/2.
MINIMUM INPUT SLEW RATE REQUIREMENT
Positive feedback from the output to the input is often used to As for all high speed comparators, a minimum slew rate must produce hysteresis in a comparator (Figure 9). The major be met to ensure that the device does not oscillate when the problem with this approach is that the amount of hysteresis input crosses the threshold. This oscillation is due in part to the varies with the output logic levels, resulting in a hysteresis that high input bandwidth of the comparator and the parasitics of is not symmetrical around zero. the package. Analog Devices recommends a slew rate of 5 V/µs or faster to ensure a clean output transition. If slew rates less Another method to implement hysteresis is generated by than 5 V/µs are used, then hysteresis should be added to reduce introducing a differential voltage between the LATCH ENABLE the oscillation. and LATCH ENABLE inputs (Figure 10). Hysteresis generated in this manner is independent of output swing and is symmetri- cal around zero. The variation of hysteresis with input voltage is shown in Figure 6. Rev. 0 | Page 10 of 16 Document Outline SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TIMING INFORMATION APPLICATION INFORMATION CLOCK TIMING RECOVERY OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE