Datasheet AD8561 (Analog Devices) - 7

ManufacturerAnalog Devices
DescriptionUltrafast 7 ns Single Supply Comparator
Pages / Page12 / 7 — AD8561. APPLICATIONS. OPTIMIZING HIGH SPEED PERFORMANCE. INCREASING …
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AD8561. APPLICATIONS. OPTIMIZING HIGH SPEED PERFORMANCE. INCREASING OUTPUT SWING. OUTPUT LOADING CONSIDERATIONS

AD8561 APPLICATIONS OPTIMIZING HIGH SPEED PERFORMANCE INCREASING OUTPUT SWING OUTPUT LOADING CONSIDERATIONS

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AD8561 APPLICATIONS
Example: A comparator compares a fast moving signal to a
OPTIMIZING HIGH SPEED PERFORMANCE
fixed 2.5 V reference. Since the comparator only needs to oper- As with any high speed comparator or amplifier, proper design ate when the signal is near 2.5 V, both signals will be within the and layout techniques should be used to ensure optimal perfor- input range (near 2.5 V and well under 3.0 V) when the com- mance from the AD8561. The performance limits of high speed parator needs to change output. circuitry can easily be a result of stray capacitance, improper Note that signals much greater than 3.0 V will result increased ground impedance or other layout issues. input currents and may cause the device to operate more slowly. Minimizing resistance from source to the input is an important The input bias current of the AD8561 is lower (–3 μA typical) consideration in maximizing the high speed operation of the than the LT1016 (+5 μA typical), and the current flows out of AD8561. Source resistance in combination with equivalent the AD8561 and into LT1016. If relatively low value resistors input capacitance could cause a lagged response at the input, and/or low impedance sources are used on the inputs, the volt- thus delaying the output. The input capacitance of the AD8561 age shift due to bias current should be small. in combination with stray capacitance from an input pin to The AD8561 (6.75 ns typical) is faster than the LT1016 (10 ns ground could result in several picofarads of equivalent capaci- typical). While this is beneficial to many systems, timing may tance. A combination of 3 kΩ source resistance and 5 pF of need to be adjusted to take advantage of the higher speed. input capacitance yields a time constant of 15 ns, which is slower than the 5 ns capability of the AD8561. Source imped- The AD8561 has slightly more output voltage swing, from 0.2 V ances should be less than 1 kΩ for the best performance. above ground to within 1.1 V of the positive supply voltage. It is also important to provide bypass capacitors for the power The AD8561 uses less current (typically 5 mA) than the LT1016 supply in a high speed application. A 1 μF electrolytic bypass (typically 25 mA). capacitor should be placed within 0.5 inches of each power supply pin, Pin 1 and Pin 4, to ground. These capacitors will
INCREASING OUTPUT SWING
reduce any potential voltage ripples from the power supply. In Although not required for normal operation, the output voltage addition, a 10 nF ceramic capacitor should be placed as close as swing of the AD8561 can be increased by connecting a 5 kΩ possible from the power supply pins to ground. These capacitors resistor from the output of the device to the V+ power supply. act as a charge reservoir for the device during high frequency This configuration can be useful in low voltage power supply switching. applications where maximizing output voltage swing is impor- tant. Adding a 5 kΩ pull-up resistor to the device’s output will A ground plane is recommended for proper high speed perfor- not adversely affect the specifications of the AD8561. mance. This can be created by using a continuous conductive plane over the surface of the circuit board, only allowing breaks
OUTPUT LOADING CONSIDERATIONS
in the plane for necessary current paths. The ground plane The AD8561 output can deliver up to 40 mA of output current provides a low inductive ground, eliminating any potential dif- without any significant increase in propagation delay. The ferences at different ground points throughout the circuit board output of the device should not be connected to more than caused from “ground bounce.” A proper ground plane also twenty (20) TTL input logic gates, or drive a load resistance minimizes the effects of stray capacitance on the circuit board. less than 100 Ω.
REPLACING THE LT1016
To ensure the best performance from the AD8561 it is impor- The AD8561 is pin compatible with the LT1016 comparator. tant to minimize capacitive loading of the output of the device. While it is easy to replace the LT1016 with the higher perfor- Capacitive loads greater than 50 pF will cause ringing on the mance AD8561, please note that there are differences, and it is output waveform and will reduce the operating bandwidth of useful to check these to ensure proper operation. the comparator. There are five major differences between the AD8561 and the
SETUP AND HOLD TIMES FOR LATCHING THE
LT1016—input voltage range, input bias currents, speed, out-
OUTPUT
put swing and power consumption. The latch input, Pin 5, can be used to retain data at the output When operated on a +5 V single supply, the LT1016 has an of the AD8561. When the voltage at the latch input goes high, input voltage range from +1.25 V to +3.5 V. The AD8561 has a the output of the device will remain constant regardless of the wider input range from 0 V to 3.0 V. Signals above 3.0 V may input voltages. The setup time for the latch is 2 ns–3 ns and the result in slower response times (see Figure 8). If both signals hold time is 3 ns. This means that to ensure data retention at exceed 3.0 V, the signals may be shifted or attenuated to bring the output, the input signal must be valid at least 5 ns before them into range, keeping in mind the note about source resis- the latch pin goes high and must remain valid at least 3 ns after tance in Optimizing High Speed Performance. If only one of the the latch pin goes high. Once the latch input voltage goes low, signals exceeds 3.0 V only slightly, and the other signal is always new output data will appear in approximately 8 ns. well within the 0 V to 3 V range, the comparator may operate A logic high for the latch input is a minimum of +2.0 V and a without changes to the circuit. logic low is a maximum of +0.8 V. This makes the latch input easily interface with TTL or CMOS logic gates. The latch circuitry in the AD8561 has no built-in hysteresis. Rev. D –7– Document Outline Features Applications General Description Pin Configurations Specifications Electrical Specifications Absolute Maximum Ratings Typical Performance Characteristics Applications Optimizing High Speed Performance Replacing the LT1016 Increasing Output Swing Output Loading Considerations Setup and Hold Times for Latching the Output Input Stage and Bias Currents Using Hysteresis SPICE Model Outline Dimensions Ordering Guide Revision History