Datasheet ADP7157 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 1.2 A, Ultralow Noise, High PSRR, Adjustable Output, RF Linear Regulator |
| Pages / Page | 23 / 5 — Data Sheet. ADP7157. ABSOLUTE MAXIMUM RATINGS. Table 4. Parameter. … |
| Revision | B |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
Data Sheet. ADP7157. ABSOLUTE MAXIMUM RATINGS. Table 4. Parameter. Rating. THERMAL DATA. THERMAL RESISTANCE
Model Line for this Datasheet
Text Version of Document
Data Sheet ADP7157 ABSOLUTE MAXIMUM RATINGS
The maximum TJ is calculated from the TA and the PD using the
Table 4.
following formula:
Parameter Rating
T VIN to Ground −0.3 V to +7 V J = TA + (PD × θJA) VREG to Ground −0.3 V to VIN or +4 V The junction to ambient thermal resistance (θJA) of the package (whichever is less) is based on modeling and calculation using a 4-layer board. The VOUT to Ground −0.3 V to VREG or +4 V junction to ambient thermal resistance is highly dependent on (whichever is less) the application and board layout. In applications where high VOUT_SENSE to Ground −0.3 V to VREG or +4 V maximum power dissipation exists, close attention to thermal (whichever is less) board design is required. The θJA value may vary, depending on VOUT to VOUT_SENSE ±0.3 V PCB material, layout, and environmental conditions. The specified BYP to VOUT ±0.3 V θJA values are based on a 4-layer, 4 in. × 3 in. circuit board. See EN to Ground −0.3 V to +7 V the JESD51-7 standard and the JESD51-9 standard for detailed BYP to Ground −0.3 V to VREG or +4 V information on the board construction. (whichever is less) REF to Ground −0.3 V to VREG or +4 V ΨJB is the junction to board thermal characterization parameter (whichever is less) with units of °C/W. ΨJB of the package is based on modeling and REF_SENSE to Ground −0.3 V to +4 V calculation using a 4-layer board. JESD51-12, Guidelines for Storage Temperature Range −65°C to +150°C Reporting and Using Electronic Package Thermal Information, Operational Junction Temperature −40°C to +125°C states that thermal characterization parameters are not the same Range as thermal resistances. ΨJB measures the component power Soldering Conditions JEDEC J-STD-020 flowing through multiple thermal paths rather than a single Stresses at or above those listed under Absolute Maximum path as in thermal resistance, θJB. Therefore, ΨJB thermal paths Ratings may cause permanent damage to the product. This is a include convection from the top of the package as wel as stress rating only; functional operation of the product at these radiation from the package, factors that make ΨJB more useful or any other conditions above those indicated in the operational in real-world applications. Use the board temperature (TB) and section of this specification is not implied. Operation beyond power dissipation (PD) to calculate the maximum junction the maximum operating conditions for extended periods may temperature (TJ) by affect product reliability. TJ = TB + (PD × ΨJB)
THERMAL DATA
See the JESD51-8 standard and the JESD51-12 standard for Absolute maximum ratings apply individually only, not in more detailed information about ΨJB. combination. The ADP7157 can be damaged when the junction
THERMAL RESISTANCE
temperature limits are exceeded. Monitoring ambient temperature θ does not guarantee that T JA, θJC, and ΨJB are specified for the worst case conditions, that J is within the specified temperature is, a device soldered in a circuit board for surface-mount limits. In applications with high power dissipation and poor packages. thermal resistance, the maximum ambient temperature may need to be derated.
Table 5. Thermal Resistance
In applications with moderate power dissipation and low
Package Type θJA θJC ΨJB Unit
printed circuit board (PCB) thermal resistance, the maximum 10-Lead LFCSP 53.8 15.6 29.1 °C/W ambient temperature can exceed the maximum limit as long as 8-Lead SOIC 50.4 42.3 30.1 °C/W the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the
ESD CAUTION
ambient temperature (TA), the power dissipation of the device (PD), and the junction to ambient thermal resistance of the package (θJA). Rev. B | Page 5 of 23 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties UNDERVOLTAGE LOCKOUT (UVLO) PROGRAMMABLE PRECISION ENABLE START-UP TIME REF, BYP, AND VREG PINS CURRENT-LIMIT AND THERMAL SHUTDOWN THERMAL CONSIDERATIONS Thermal Characterization Parameter (ΨJB) PSRR PERFORMANCE PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
The maximum TJ is calculated from the TA and the PD using the
Table 4.
following formula:
Parameter Rating
T VIN to Ground −0.3 V to +7 V J = TA + (PD × θJA) VREG to Ground −0.3 V to VIN or +4 V The junction to ambient thermal resistance (θJA) of the package (whichever is less) is based on modeling and calculation using a 4-layer board. The VOUT to Ground −0.3 V to VREG or +4 V junction to ambient thermal resistance is highly dependent on (whichever is less) the application and board layout. In applications where high VOUT_SENSE to Ground −0.3 V to VREG or +4 V maximum power dissipation exists, close attention to thermal (whichever is less) board design is required. The θJA value may vary, depending on VOUT to VOUT_SENSE ±0.3 V PCB material, layout, and environmental conditions. The specified BYP to VOUT ±0.3 V θJA values are based on a 4-layer, 4 in. × 3 in. circuit board. See EN to Ground −0.3 V to +7 V the JESD51-7 standard and the JESD51-9 standard for detailed BYP to Ground −0.3 V to VREG or +4 V information on the board construction. (whichever is less) REF to Ground −0.3 V to VREG or +4 V ΨJB is the junction to board thermal characterization parameter (whichever is less) with units of °C/W. ΨJB of the package is based on modeling and REF_SENSE to Ground −0.3 V to +4 V calculation using a 4-layer board. JESD51-12, Guidelines for Storage Temperature Range −65°C to +150°C Reporting and Using Electronic Package Thermal Information, Operational Junction Temperature −40°C to +125°C states that thermal characterization parameters are not the same Range as thermal resistances. ΨJB measures the component power Soldering Conditions JEDEC J-STD-020 flowing through multiple thermal paths rather than a single Stresses at or above those listed under Absolute Maximum path as in thermal resistance, θJB. Therefore, ΨJB thermal paths Ratings may cause permanent damage to the product. This is a include convection from the top of the package as wel as stress rating only; functional operation of the product at these radiation from the package, factors that make ΨJB more useful or any other conditions above those indicated in the operational in real-world applications. Use the board temperature (TB) and section of this specification is not implied. Operation beyond power dissipation (PD) to calculate the maximum junction the maximum operating conditions for extended periods may temperature (TJ) by affect product reliability. TJ = TB + (PD × ΨJB)
THERMAL DATA
See the JESD51-8 standard and the JESD51-12 standard for Absolute maximum ratings apply individually only, not in more detailed information about ΨJB. combination. The ADP7157 can be damaged when the junction
THERMAL RESISTANCE
temperature limits are exceeded. Monitoring ambient temperature θ does not guarantee that T JA, θJC, and ΨJB are specified for the worst case conditions, that J is within the specified temperature is, a device soldered in a circuit board for surface-mount limits. In applications with high power dissipation and poor packages. thermal resistance, the maximum ambient temperature may need to be derated.
Table 5. Thermal Resistance
In applications with moderate power dissipation and low
Package Type θJA θJC ΨJB Unit
printed circuit board (PCB) thermal resistance, the maximum 10-Lead LFCSP 53.8 15.6 29.1 °C/W ambient temperature can exceed the maximum limit as long as 8-Lead SOIC 50.4 42.3 30.1 °C/W the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the
ESD CAUTION
ambient temperature (TA), the power dissipation of the device (PD), and the junction to ambient thermal resistance of the package (θJA). Rev. B | Page 5 of 23 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties UNDERVOLTAGE LOCKOUT (UVLO) PROGRAMMABLE PRECISION ENABLE START-UP TIME REF, BYP, AND VREG PINS CURRENT-LIMIT AND THERMAL SHUTDOWN THERMAL CONSIDERATIONS Thermal Characterization Parameter (ΨJB) PSRR PERFORMANCE PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
