Datasheet AD8228 (Analog Devices) - 9

AD8228 TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.
MEAN: –5.5 100 MEAN: 0.20 70 SD: 12.4 SD: 0.12 60 80 50 60 S 40 S T T HI HI 30 40 20 20 10 0 0
47
–100 –50 0 50 100
430
–1.0 –0.5 0 0.5 1.0 1.5
0 5- 5-
G10 SYSTEM V
03 03
OS RTI @ 15V (µV) G100 SYSTEM V
07
OS DRIFT RTI (µV)
07 Figure 3. Typical Distribution of Input Offset Voltage (G = 10) Figure 6. Typical Distribution of Input Offset Voltage Drift (G = 100)
100 60 MEAN: –0.079 MEAN: 0.29 SD: 0.27 SD: 0.27 50 80 40 60 S S T T HI 30 HI 40 20 20 10 0 0
48
–1.5 –1.0 –0.5 0 0.5 1.0 1.5
450
–3 –2 –1 0 1 2 3
0 5- 5-
G10 SYSTEM V
03 03
OS DRIFT RTI (µV) CMRR G100 RTI (µV/V)
07 07 Figure 4. Typical Distribution of Input Offset Voltage Drift (G = 10) Figure 7. Typical Distribution for CMR (G = 100)
MEAN: 7.1 MEAN: 0.42 SD: 10.1 120 SD: 0.08 80 100 60 80 S S T T HI HI 60 40 40 20 20 0 0
49
–100 –50 0 50 100
460
–0.5 0 0.5 1.0 1.5
0 5- 5-
G100 SYSTEM V
03
NEG I
03
OS RTI @ 15V (µV) BIAS CURRENTS ±15V (nA)
07 07 Figure 5. Typical Distribution of Input Offset Voltage (G = 100) Figure 8. Typical Distribution of Input Bias Current Rev. 0 | Page 9 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION CONNECTION DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GAIN = 10 GAIN = 100 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARCHITECTURE SETTING THE GAIN COMMON-MODE INPUT VOLTAGE RANGE REFERENCE TERMINAL LAYOUT Common-Mode Rejection Ratio over Frequency Power Supplies References Input Bias Current Return Path INPUT PROTECTION Input Voltages Beyond the Rails Large Differential Voltages When G = 100 RADIO FREQUENCY INTERFERENCE (RFI) APPLICATIONS INFORMATION DIFFERENTIAL DRIVE PRECISION STRAIN GAGE DRIVING A DIFFERENTIAL ADC OUTLINE DIMENSIONS ORDERING GUIDE