Datasheet AD8250 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 10 MHz G = 1, 2, 5, 10 iCMOS Programmable Gain Instrumentation Amplifier |
| Pages / Page | 24 / 6 — AD8250. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 3. Parameter. Rating. … |
| Revision | C |
| File Format / Size | PDF / 848 Kb |
| Document Language | English |
AD8250. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 3. Parameter. Rating. MAXIMUM POWER DISSIPATION. 2.00. ) 1.75. N 1.50. T PA. 1.25. ISSI
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AD8250 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3.
The power dissipated in the package (PD) is the sum of the
Parameter Rating
quiescent power dissipation and the power dissipated in the package due to the load drive for al outputs. The quiescent Supply Voltage ±17 V power is the voltage between the supply pins (V Power Dissipation See Figure 4 S) times the quiescent current (I Output Short-Circuit Current Indefinite1 S). Assuming that the load (RL) is referenced to midsupply, the total drive power is V Common-Mode Input Voltage +V S/2 × IOUT, some of which S + 13 V, −VS − 13 V is dissipated in the package and some in the load (V Differential Input Voltage +V OUT × IOUT). S + 13 V, −VS − 13 V2 Digital Logic Inputs ±VS The difference between the total drive power and the load Storage Temperature Range −65°C to +125°C power is the drive power dissipated in the package. Operating Temperature Range3 −40°C to +85°C P Lead Temperature (Soldering, 10 sec) 300°C D = Quiescent Power + (Total Drive Power − Load Power) Junction Temperature 140°C 2 P = (V × I ) S V OU V T OU V T + × – θ D S S JA (Four-Layer JEDEC Standard Board) 112°C/W 2 RL RL Package Glass Transition Temperature 140°C In single-supply operation with RL referenced to −VS, the worst 1 Assumes that the load is referenced to midsupply. 2 Current must be kept to less than 6 mA. case is VOUT = VS/2. 3 Temperature for specified performance is −40°C to +85°C. For performance to 125°C, see the Typical Performance Characteristics section. Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads Stresses above those listed under Absolute Maximum Ratings from metal traces, through holes, ground, and power planes may cause permanent damage to the device. This is a stress reduces the θJA. rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of Figure 4 shows the maximum safe power dissipation in the this specification is not implied. Exposure to absolute maximum package vs. the ambient temperature on a four-layer JEDEC rating conditions for extended periods may affect device reliability. standard board.
MAXIMUM POWER DISSIPATION 2.00
The maximum safe power dissipation in the AD8250 package is
) 1.75
limited by the associated rise in junction temperature (T
(W
J) on
N 1.50 IO
the die. The plastic encapsulating the die locally reaches the
T PA
junction temperature. At approximately 140°C, which is the
1.25 ISSI
glass transition temperature, the plastic changes its properties.
D 1.00
Even temporarily exceeding this temperature limit can change
ER W
the stresses that the package exerts on the die, permanently
0.75 M PO
shifting the parametric performance of the AD8250. Exceeding
MU 0.50 XI
a junction temperature of 140°C for an extended period can
MA 0.25
result in changes in silicon devices, potentially causing failure.
0
The still-air thermal properties of the package and PCB (θJA),
–40 –20 0 20 40 60 80 100 120
004 the ambient temperature (T
AMBIENT TEMPERATURE (°C)
A), and the total power dissipated in 06288- the package (P Figure 4. Maximum Power Dissipation vs. Ambient Temperature D) determine the junction temperature of the die. The junction temperature is calculated as
ESD CAUTION
TJ = TA + (PD × θJA) Rev. C | Page 6 of 24 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Diagram Absolute Maximum Ratings Maximum Power Dissipation ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Gain Selection Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode Power Supply Regulation and Bypassing Input Bias Current Return Path Input Protection Reference Terminal Common-Mode Input Voltage Range Layout Grounding Coupling Noise Common-Mode Rejection RF Interference Driving an ADC Applications Differential Output Setting Gains with a Microcontroller Data Acquisition Outline Dimensions Ordering Guide
AD8250 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3.
The power dissipated in the package (PD) is the sum of the
Parameter Rating
quiescent power dissipation and the power dissipated in the package due to the load drive for al outputs. The quiescent Supply Voltage ±17 V power is the voltage between the supply pins (V Power Dissipation See Figure 4 S) times the quiescent current (I Output Short-Circuit Current Indefinite1 S). Assuming that the load (RL) is referenced to midsupply, the total drive power is V Common-Mode Input Voltage +V S/2 × IOUT, some of which S + 13 V, −VS − 13 V is dissipated in the package and some in the load (V Differential Input Voltage +V OUT × IOUT). S + 13 V, −VS − 13 V2 Digital Logic Inputs ±VS The difference between the total drive power and the load Storage Temperature Range −65°C to +125°C power is the drive power dissipated in the package. Operating Temperature Range3 −40°C to +85°C P Lead Temperature (Soldering, 10 sec) 300°C D = Quiescent Power + (Total Drive Power − Load Power) Junction Temperature 140°C 2 P = (V × I ) S V OU V T OU V T + × – θ D S S JA (Four-Layer JEDEC Standard Board) 112°C/W 2 RL RL Package Glass Transition Temperature 140°C In single-supply operation with RL referenced to −VS, the worst 1 Assumes that the load is referenced to midsupply. 2 Current must be kept to less than 6 mA. case is VOUT = VS/2. 3 Temperature for specified performance is −40°C to +85°C. For performance to 125°C, see the Typical Performance Characteristics section. Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads Stresses above those listed under Absolute Maximum Ratings from metal traces, through holes, ground, and power planes may cause permanent damage to the device. This is a stress reduces the θJA. rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of Figure 4 shows the maximum safe power dissipation in the this specification is not implied. Exposure to absolute maximum package vs. the ambient temperature on a four-layer JEDEC rating conditions for extended periods may affect device reliability. standard board.
MAXIMUM POWER DISSIPATION 2.00
The maximum safe power dissipation in the AD8250 package is
) 1.75
limited by the associated rise in junction temperature (T
(W
J) on
N 1.50 IO
the die. The plastic encapsulating the die locally reaches the
T PA
junction temperature. At approximately 140°C, which is the
1.25 ISSI
glass transition temperature, the plastic changes its properties.
D 1.00
Even temporarily exceeding this temperature limit can change
ER W
the stresses that the package exerts on the die, permanently
0.75 M PO
shifting the parametric performance of the AD8250. Exceeding
MU 0.50 XI
a junction temperature of 140°C for an extended period can
MA 0.25
result in changes in silicon devices, potentially causing failure.
0
The still-air thermal properties of the package and PCB (θJA),
–40 –20 0 20 40 60 80 100 120
004 the ambient temperature (T
AMBIENT TEMPERATURE (°C)
A), and the total power dissipated in 06288- the package (P Figure 4. Maximum Power Dissipation vs. Ambient Temperature D) determine the junction temperature of the die. The junction temperature is calculated as
ESD CAUTION
TJ = TA + (PD × θJA) Rev. C | Page 6 of 24 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Diagram Absolute Maximum Ratings Maximum Power Dissipation ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Gain Selection Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode Power Supply Regulation and Bypassing Input Bias Current Return Path Input Protection Reference Terminal Common-Mode Input Voltage Range Layout Grounding Coupling Noise Common-Mode Rejection RF Interference Driving an ADC Applications Differential Output Setting Gains with a Microcontroller Data Acquisition Outline Dimensions Ordering Guide
