Datasheet ADSP-21566, ADSP-21567, ADSP-21569 (Analog Devices) - 7

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ADSP-21566/21567/21569 Core Timer
Additionally, the double-precision floating-point instruction set is new to the SHARC+ core, as compared with the previous The SHARC+ processor core includes an extra timer. This extra SHARC core. timer is clocked by the internal processor clock and is typically used as a system tick clock for generating periodic operating
Variable Instruction Set Architecture (VISA)
system interrupts. In addition to supporting the standard 48-bit instructions from
Data Register File
previous SHARC core processors, the SHARC+ core processors support 16-bit and 32-bit opcodes for many instructions, for- Each processing element contains a general-purpose data regis- merly 48-bit in the ISA. This variable instruction set ter file. The register files transfer data between the computation architecture (VISA) feature drops redundant or unused bits units and the data buses, and store intermediate results. These within the 48-bit instruction to create more efficient and com- 10-port, 32-register register files (16 primary, 16 secondary), pact code. The program sequencer supports fetching these combined with the enhanced Harvard architecture of the pro- 16-bit and 32-bit instructions from both internal and external cessor, allow unconstrained data flow between computation memories. VISA is not an operating mode; rather, it is address units and internal memory. The registers in the PEx data regis- dependent (refer to the ISA/VISA address spaces in Table 5). ter file are referred to as R0–R15 and in the PEy data register file Finally, the processor allows jumps between ISA and VISA as S0–S15. instruction fetches.
Context Switch Single-Cycle Fetch of Instructional Four Operands
Many of the registers of the processor have secondary registers The ADSP-2156x processors feature an enhanced Harvard that can activate during interrupt servicing for a fast context architecture in which the DM bus transfers data and the PM bus switch. The data, DAG, and multiplier result registers have sec- transfers both instructions and data. ondary registers. The primary registers are active at reset, whereas control bits in MODE1 activate the secondary registers. With the separate program memory bus, data memory buses, and on-chip instruction conflict cache, the processor can simul-
Universal Registers
taneously fetch four operands (two over each data bus) and one General-purpose tasks use the universal registers. The four uni- instruction from the conflict cache in a single cycle. versal status (USTAT) registers allow easy bit manipulations
Core Event Controller (CEC)
(set, clear, toggle, test, XOR) for all control and status peripheral registers. The SHARC+ core event controller (CEC) can be configured to service various interrupts generated by the core (including The data bus exchange register (PX) permits data to pass arithmetic and circular buffer instruction flow exceptions) and between the 64-bit PM data bus and the 64-bit DM data bus or system event controller (SEC) events (peripheral interrupt between the 40-bit register file and the PM or DM data bus. request, debug or monitor, and software-raised), responding These registers contain hardware to handle the data width only to interrupts enabled in the IMASK register. The output of difference. the SEC is forwarded to the CEC to respond directly to any
Data Address Generators (DAG) With Zero Overhead
enabled system interrupts. For all SEC channels, the processor
Hardware Circular Buffer Support
automatically stacks the arithmetic status (ASTATx and ASTATy) registers and mode (MODE1) register in parallel with For indirect addressing and implementing circular data buffers interrupt servicing. in hardware, the ADSP-2156x processor uses two data address generators (DAGs). Circular buffers allow efficient program-
Instruction Conflict Cache
ming of delay lines and other data structures required in digital The processors include a 32-entry instruction cache that enables signal processing and are commonly used in digital filters and three-bus operation for fetching an instruction and four data fast Fourier transforms (FFT). The DAGs contain sufficient reg- values. The cache is selective—only the instructions that require isters to allow the creation of up to 32 circular buffers (16 fetches conflict with the PM bus data access cache. This cache primary register sets and 16 secondary sets). The DAGs auto- allows full speed execution of core looped operations, such as matically handle address pointer wraparound, reduce overhead, digital filter multiply accumulates and FFT butterfly processing. increase performance, and simplify implementation. Circular The conflict cache serves for bus conflicts within the SHARC+ buffers can start and end at any memory location. core only.
Flexible Instruction Set Architecture (ISA) Branch Target Buffer (BTB)/Branch Predictor (BP)
The flexible instruction set architecture (ISA), a 48-bit instruc- Implementation of a hardware-based branch predictor (BP) and tion word, accommodates various parallel operations for branch target buffer (BTB) reduce branch delay. The program concise programming. For example, the processors can condi- sequencer supports efficient branching using the BTB for condi- tionally execute a multiply, an add, and a subtract in both tional and unconditional instructions. processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. Rev. 0 | Page 7 of 98 | March 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Code (ECC) Protected L2 Memories Parity Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Data Transmission Current Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Planned Automotive Production Products Planned Production Products Ordering Guide