Datasheet ADSP-21369 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | SHARC Processor |
| Pages / Page | 60 / 6 — ADSP-21369. On-Chip Memory. On-Chip Memory Bandwidth. ROM-Based Security. … |
| Revision | H |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
ADSP-21369. On-Chip Memory. On-Chip Memory Bandwidth. ROM-Based Security. Table 3. Internal Memory Space 1
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ADSP-21369 On-Chip Memory
Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two The processors contain two megabits of internal RAM and six data transfers. In this case, the instruction must be available in megabits of internal mask-programmable ROM. Each block can the cache. be configured for different combinations of code and data stor- age (see Table 3). Each memory block supports single-cycle,
On-Chip Memory Bandwidth
independent accesses by the core processor and I/O processor. The memory architecture, in combination with its separate on- The internal memory architecture allows programs to have four chip buses, allows two data transfers from the core and one accesses at the same time to any of the four blocks (assuming from the I/O processor, in a single cycle. there are no block conflicts). The total bandwidth is realized using the DMD and PMD buses (2 × 64-bit, core CLK) and the The SRAM can be configured as a maximum of 64k words of IOD0/1 buses (2 × 32-bit, PCLK). 32-bit data, 128k words of 16-bit data, 42k words of 48-bit instructions (or 40-bit data), or combinations of different word
ROM-Based Security
sizes up to two megabits. All of the memory can be accessed as The processor has a ROM security feature that provides hard- 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point ware support for securing user software code by preventing storage format is supported that effectively doubles the amount unauthorized reading from the internal code when enabled. of data that can be stored on-chip. Conversion between the When using this feature, the processor does not boot-load any 32-bit floating-point and 16-bit floating-point formats is per- external code, executing exclusively from internal ROM. Addi- formed in a single instruction. While each memory block can tionally, the processor is not freely accessible via the JTAG port. store combinations of code and data, accesses are most efficient Instead, a unique 64-bit key, which must be scanned in through when one block stores data using the DM bus for transfers, and the JTAG or test access port will be assigned to each customer. the other block stores instructions and data using the PM bus The device will ignore a wrong key. Emulation features and for transfers. external boot modes are only available after the correct key is scanned.
Table 3. Internal Memory Space 1 IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)
Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) 0x0004 0000–0x0004 BFFF 0x0008 0000–0x0008 FFFF 0x0008 0000–0x0009 7FFF 0x0010 0000–0x0012 FFFF Reserved Reserved Reserved Reserved 0x0004 F000–0x0004 FFFF 0x0009 4000–0x0009 FFFF 0x0009 E000–0x0009 FFFF 0x0013 C000–0x0013 FFFF Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM 0x0004 C000–0x0004 EFFF 0x0009 0000–0x0009 3FFF 0x0009 8000–0x0009 DFFF 0x0013 0000–0x0013 BFFF Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) 0x0005 0000–0x0005 BFFF 0x000A 0000–0x000A FFFF 0x000A 0000–0x000B 7FFF 0x0014 0000–0x0016 FFFF Reserved Reserved Reserved Reserved 0x0005 F000–0x0005 FFFF 0x000B 4000–0x000B FFFF 0x000B E000–0x000B FFFF 0x0017 C000–0x0017 FFFF Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM 0x0005 C000–0x0005 EFFF 0x000B 0000–0x000B 3FFF 0x000B 8000–0x000B DFFF 0x0017 0000–0x0017 BFFF Block 2 SRAM Block 2 SRAM Block 2 SRAM Block 2 SRAM 0x0006 0000–0x0006 0FFF 0x000C 0000–0x000C 1554 0x000C 0000–0x000C 1FFF 0x0018 0000–0x0018 3FFF Reserved Reserved Reserved Reserved 0x0006 1000– 0x0006 FFFF 0x000C 1555–0x000C 3FFF 0x000C 2000–0x000D FFFF 0x0018 4000–0x001B FFFF Block 3 SRAM Block 3 SRAM Block 3 SRAM Block 3 SRAM 0x0007 0000–0x0007 0FFF 0x000E 0000–0x000E 1554 0x000E 0000–0x000E 1FFF 0x001C 0000–0x001C 3FFF Reserved Reserved Reserved Reserved 0x0007 1000–0x0007 FFFF 0x000E 1555–0x000F FFFF 0x000E 2000–0x000F FFFF 0x001C 4000–0x001F FFFF 1 The processor includes a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details. Rev. H | Page 6 of 60 | March 2019 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Shared External Memory External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Synchronous/Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Memory Read Memory Write Asynchronous Memory Interface (AMI) Enable/Disable Shared Memory Bus Request Serial Ports Input Data Port Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 256-Ball BGA_ED Pinout 208-Lead LQFP_EP Pinout Package Dimensions Surface-Mount Design Ordering Guide
ADSP-21369 On-Chip Memory
Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two The processors contain two megabits of internal RAM and six data transfers. In this case, the instruction must be available in megabits of internal mask-programmable ROM. Each block can the cache. be configured for different combinations of code and data stor- age (see Table 3). Each memory block supports single-cycle,
On-Chip Memory Bandwidth
independent accesses by the core processor and I/O processor. The memory architecture, in combination with its separate on- The internal memory architecture allows programs to have four chip buses, allows two data transfers from the core and one accesses at the same time to any of the four blocks (assuming from the I/O processor, in a single cycle. there are no block conflicts). The total bandwidth is realized using the DMD and PMD buses (2 × 64-bit, core CLK) and the The SRAM can be configured as a maximum of 64k words of IOD0/1 buses (2 × 32-bit, PCLK). 32-bit data, 128k words of 16-bit data, 42k words of 48-bit instructions (or 40-bit data), or combinations of different word
ROM-Based Security
sizes up to two megabits. All of the memory can be accessed as The processor has a ROM security feature that provides hard- 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point ware support for securing user software code by preventing storage format is supported that effectively doubles the amount unauthorized reading from the internal code when enabled. of data that can be stored on-chip. Conversion between the When using this feature, the processor does not boot-load any 32-bit floating-point and 16-bit floating-point formats is per- external code, executing exclusively from internal ROM. Addi- formed in a single instruction. While each memory block can tionally, the processor is not freely accessible via the JTAG port. store combinations of code and data, accesses are most efficient Instead, a unique 64-bit key, which must be scanned in through when one block stores data using the DM bus for transfers, and the JTAG or test access port will be assigned to each customer. the other block stores instructions and data using the PM bus The device will ignore a wrong key. Emulation features and for transfers. external boot modes are only available after the correct key is scanned.
Table 3. Internal Memory Space 1 IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)
Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) 0x0004 0000–0x0004 BFFF 0x0008 0000–0x0008 FFFF 0x0008 0000–0x0009 7FFF 0x0010 0000–0x0012 FFFF Reserved Reserved Reserved Reserved 0x0004 F000–0x0004 FFFF 0x0009 4000–0x0009 FFFF 0x0009 E000–0x0009 FFFF 0x0013 C000–0x0013 FFFF Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM 0x0004 C000–0x0004 EFFF 0x0009 0000–0x0009 3FFF 0x0009 8000–0x0009 DFFF 0x0013 0000–0x0013 BFFF Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) 0x0005 0000–0x0005 BFFF 0x000A 0000–0x000A FFFF 0x000A 0000–0x000B 7FFF 0x0014 0000–0x0016 FFFF Reserved Reserved Reserved Reserved 0x0005 F000–0x0005 FFFF 0x000B 4000–0x000B FFFF 0x000B E000–0x000B FFFF 0x0017 C000–0x0017 FFFF Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM 0x0005 C000–0x0005 EFFF 0x000B 0000–0x000B 3FFF 0x000B 8000–0x000B DFFF 0x0017 0000–0x0017 BFFF Block 2 SRAM Block 2 SRAM Block 2 SRAM Block 2 SRAM 0x0006 0000–0x0006 0FFF 0x000C 0000–0x000C 1554 0x000C 0000–0x000C 1FFF 0x0018 0000–0x0018 3FFF Reserved Reserved Reserved Reserved 0x0006 1000– 0x0006 FFFF 0x000C 1555–0x000C 3FFF 0x000C 2000–0x000D FFFF 0x0018 4000–0x001B FFFF Block 3 SRAM Block 3 SRAM Block 3 SRAM Block 3 SRAM 0x0007 0000–0x0007 0FFF 0x000E 0000–0x000E 1554 0x000E 0000–0x000E 1FFF 0x001C 0000–0x001C 3FFF Reserved Reserved Reserved Reserved 0x0007 1000–0x0007 FFFF 0x000E 1555–0x000F FFFF 0x000E 2000–0x000F FFFF 0x001C 4000–0x001F FFFF 1 The processor includes a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details. Rev. H | Page 6 of 60 | March 2019 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Shared External Memory External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Synchronous/Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Memory Read Memory Write Asynchronous Memory Interface (AMI) Enable/Disable Shared Memory Bus Request Serial Ports Input Data Port Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 256-Ball BGA_ED Pinout 208-Lead LQFP_EP Pinout Package Dimensions Surface-Mount Design Ordering Guide
