Datasheet AD1835A (Analog Devices) - 7

ManufacturerAnalog Devices
Description2 ADC, 8 DAC, 96 kHz, 24-Bit Sigma Delta Codec
Pages / Page24 / 7 — AD1835A. PIN CONFIGURATION. DGND. CCLK. COUT. ASDATA. ODVDD. MCLK. …
RevisionA
File Format / SizePDF / 282 Kb
Document LanguageEnglish

AD1835A. PIN CONFIGURATION. DGND. CCLK. COUT. ASDATA. ODVDD. MCLK. ALRCLK. ABCLK. DSDATA4. DSDATA3. DSDATA2. DSDATA1. DVDD. 39 DVDD. CLATCH. 38 DBCLK. CIN

AD1835A PIN CONFIGURATION DGND CCLK COUT ASDATA ODVDD MCLK ALRCLK ABCLK DSDATA4 DSDATA3 DSDATA2 DSDATA1 DVDD 39 DVDD CLATCH 38 DBCLK CIN

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Text Version of Document

AD1835A PIN CONFIGURATION DGND CCLK COUT ASDATA ODVDD MCLK ALRCLK ABCLK DSDATA4 DSDATA3 DSDATA2 DSDATA1 DGND 52 51 50 49 48 47 46 45 44 43 42 41 40 DVDD 1 39 DVDD CLATCH 2 38 DBCLK CIN 3 37 DLRCLK PD/RST 4 36 M/S AGND 5 35 AGND OUTLN1 6 34 OUTRP4 AD1835A TOP VIEW OUTLP1 7 33 OUTRN4 (Not to Scale) OUTRN1 8 32 OUTLP4 OUTRP1 9 31 OUTLN4 AGND 10 30 AGND AVDD 11 29 AVDD OUTLN2 12 28 OUTRP3 OUTLP2 13 27 OUTRN3 14 15 16 17 18 19 20 21 22 23 24 25 26 AGND FILTD FILTR AVDD AGND ADCLN ADCLP ADCRN ADCRP OUTRN2 OUTRP2 OUTLN3 OUTLP3 PIN FUNCTION DESCRIPTIONS Input/ Pin Number Mnemonic Output Description
1, 39 DVDD Digital Power Supply. Connect to digital 5 V supply. 2 CLATCH I Latch Input for Control Data. 3 CIN I Serial Control Input. 4 PD/RST I Power-Down/Reset. 5, 10, 16, 24, 30, 35 AGND Analog Ground. 6, 12, 25, 31 OUTLNx O DACx Left Channel Negative Output. 7, 13, 26, 32 OUTLPx O DACx Left Channel Positive Output. 8, 14, 27, 33 OUTRNx O DACx Right Channel Negative Output. 9, 15, 28, 34 OUTRPx O DACx Right Channel Positive Output. 11, 19, 29 AVDD Analog Power Supply. Connect to analog 5 V supply. 17 FILTD Filter Capacitor Connection. Recommended 10 µF/100 nF. 18 FILTR Reference Filter Capacitor Connection. Recommended 10 µF/100 nF. 20 ADCLN I ADC Left Channel Negative Input. 21 ADCLP I ADC Left Channel Positive Input. 22 ADCRN I ADC Right Channel Negative Input. 23 ADCRP I ADC Right Channel Positive Input. 36 M/S I ADC Master/Slave Select. 37 DLRCLK I/O DAC LR Clock. 38 DBCLK I/O DAC Bit Clock. 40, 52 DGND Digital Ground. 41 to 44 DSDATAx I DACx Input Data (Left and Right Channels). 45 ABCLK I/O ADC Bit Clock. 46 ALRCLK I/O ADC LR Clock. 47 MCLK I Master Clock Input. 48 ODVDD Digital Output Driver Power Supply. 49 ASDATA O ADC Serial Data Output. 50 COUT O Output for Control Data. 51 CCLK I Control Clock Input for Control Data. REV. A –7– Document Outline FEATURES APPLICATIONS PRODUCT OVERVIEW FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS TEMPERATURE RANGE ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics DEFINITIONS Dynamic Range Signal-to-(Total Harmonic Distortion + Noise)[S/(THD + N)] Pass Band Pass-Band Ripple Stop Band Gain Error Interchannel Gain Mismatch Gain Drift Crosstalk (EIAJ Method) Power Supply Rejection Group Delay Group Delay Variation GLOSSARY FUNCTIONAL OVERVIEW ADCs DACs DAC and ADC Coding AD1835A CLOCKING SCHEME Selecting DAC Sampling Rate Selecting an ADC Sample Rate RESET and Power-Down Power Supply and Voltage Reference Serial Control Port Serial Data Ports—Data Format Packed Modes Auxiliary (TDM) Mode CONTROL/STATUS REGISTERS DAC Control Registers Sample Rate Power-Down/Reset DAC Data-Word Width DAC Data Format De-emphasis Mute DAC Stereo Replicate DAC Volume Control ADC Control Registers ADC Peak Level Sample Rate ADC Power-Down High-Pass Filter ADC Data-Word Width ADC Data Format Master/Slave Auxiliary Mode ADC Peak Readback CASCADE MODE Dual AD1835A Cascade OUTLINE DIMENSIONS Revision History