Datasheet LTC3882-1 (Analog Devices) - 68
| Manufacturer | Analog Devices |
| Description | Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management |
| Pages / Page | 108 / 68 — APPLICATIONS INFORMATION |
| Revision | B |
| File Format / Size | PDF / 3.3 Mb |
| Document Language | English |
APPLICATIONS INFORMATION
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Text Version of Document
LTC3882-1
APPLICATIONS INFORMATION
The frequency and phase are also set by EEPROM values. A loop crossover frequency of 100kHz provides good Assume that solution footprint or vertical clearance is an transient performance while still being well below the issue, so operating frequency will need to be increased switching frequency of the converter. The values of R29, in an effort to minimize inductor value (size). This choice R30 and C25 to C27 were determined to produce a nomi- could also result from the need to have above average nal system phase margin of about 65° at this bandwidth. transient performance, although efficiency may be re- For the DCR sense filter network, R = 3.09k and C = 220nF duced slightly. FREQUENCY_SWITCH is set to 1.0MHz. are chosen to match the L/DCR time constant of the induc- As a 2-phase system, MFR_PWM_CONFIG_LTC3882-1 tor. PolyPhase connections (I is programmed to 0x14 to put Channel 0 phase at 0° and AVG, et al) are shown in the schematic to ensure good output current sharing between Channel 1 phase at 180°. This produces the lowest input the two power stages. ripple possible with this configuration and allows this output to synchronize with other rails via SHARE_CLK. External temperature sense will employ an accurate ∆VBE method, and Q1 and Q2 serve to sense the temperature of The design will plan on a nominal output ripple of 70% of L1 and L2, respectively. These components will be located IOUT to minimize the magnetics volume, and the inductance immediately adjacent to their chokes and the 10nF filter value is chosen based on this assumption. Each channel capacitors placed with the BJTs. supplies an average 20A to the output at full load, result- ing in a ripple of 14AP-P. A 200nH inductor per phase Resistor configuration is used on the ASELn pins to pro- would create this peak-to-peak ripple at 1.0MHz. A Pulse gram PMBus address (MFR_ADDRESS) to 0x4C. Each PA0513.22LT 210nH inductor with a DCR of 0.32mΩ LTC3882-1 must be configured for a unique address. typical is selected. Setting IOUT_FAULT_LIMIT to 35A per Using both ASELn pins to accomplish this programming phase leaves plenty of headroom for transient conditions is recommended for simpliest in-system programming. while still adequately protecting against the rated inductor Check the selected address to avoid collision with global saturation current of 45A at temperature. addresses other any other specific devices. Identical MFR_RAIL_ADDRESS can be set in EEPROM for both For top and bottom power FETs, the 40V rated Infineon channels to allow single-command control of common BSC050N04LSG and BSC010N04LS are chosen, respec- rail parameters such as IOUT_OC_FAULT_LIMIT. The tively. These afford both low RDS(ON) and low gate charge LTC3882-1 also responds to 7-bit global addresses 0x5A QG. Two of each of these could be paralleled to achieve and 0x5B. MFR_ADDRESS and MFR_RAIL_ADDRESS improved efficiency at full load, if desired. should not be set to either of these values. The LTC4449 gate driver is chosen for its fast response PMBus connection (three signals), as well as shared (13ns), suitable gate drive, VIN capability (38V) and the RUN control and fault propagation (FAULT) are provided. ease with which it can be interfaced to the LTC3882-1. Basic SYNC can be used to synchronize other PWMs to this three-state control, CCM operation, fast boost refresh, low rail if required. VOUT range and digital output voltage servo are selected by programming MFR_PWM_MODE_LTC3882-1 to 0xC0 Pull-ups are provided on all these shared open-drain signals for both channels. assuming a maximum 100pF line load and PMBus rate of 100kHz. These pins should not be left floating. Termina- For input filtering, a 47μF SUNCON capacitor and four tion to 3.3V ensures the absolute maximum ratings for 22μF ceramic capacitors are selected to provide accept- the pins are not exceeded. All other operating parameters able AC impedance against the designed converter ripple such as soft start/stop and desired faults responses are current. Four 470μF 9mΩ POSCAPs and two 100μF programmed via PMBus command values stored in internal ceramic capacitors are chosen for the output to maintain LTC3882-1 EEPROM. supply regulation during severe transient conditions and to minimize output voltage ripple. Rev B 68 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuit Timing Diagram Operation Overview Main Control Loop Power-Up and Initialization Soft-Start Time-Based Output Sequencing Output Ramping Control Voltage-Based Output Sequencing Minimum Output Disable Times Output Short Cycle Light Load Current Operation Switching Frequency and Phase PolyPhase Load Sharing Active Voltage Positioning Input Supply Monitoring Output Voltage Sensing and Monitoring Output Current Sensing and Monitoring External and Internal Temperature Sense Resistor Configuration Pins Internal EEPROM with CRC and ECC Fault Detection Input Supply Faults Hardwired PWM Response to VOUT Faults Power Good Indication (Master) Power Good Indication (Slave) Hardwired PWM Response to IOUT Faults Hardwired PWM Response to Temperature Faults Hardwired PWM Response to Timing Faults External Faults Fault Handling Status Registers and ALERT Masking FAULT Pin I/O Fault Logging Factory Default Operation Serial Interface Serial Bus Addressing Serial Bus Timeout Serial Communication Errors PMBus Command Summary PMBus Commands Data Formats Applications Information Efficiency Considerations PWM Frequency and Inductor Selection Power MOSFET Selection MOSFET Driver Selection Using PWM Protocols CIN Selection COUT Selection Feedback Loop Compensation PCB Layout Considerations Output Current Sensing Output Voltage Sensing Soft-Start and Stop Time-Based Output Sequencing and Ramping Voltage-Based Output Sequencing Using Output Voltage Servo Using AVP PWM Frequency Synchronization PolyPhase Operation and Load Sharing External Temperature Sense Resistor Configuration Pins Internal Regulator Outputs IC Junction Temperature Derating EEPROM Retention at Temperature Configuring Open-Drain Pins PMBus Communication and Command Processing Status and Fault Log Management LTpowerPlay – An Interactive Digital Power GUI Interfacing to the DC1613 Design Example PMBus COMMAND DETAILS Addressing and Write Protect PAGE PAGE_PLUS_WRITE PAGE_PLUS_READ WRITE_PROTECT MFR_ADDRESS MFR_RAIL_ADDRESS General Device Configuration PMBUS_REVISION CAPABILITY On, Off and Margin Control ON_OFF_CONFIG MFR_CONFIG_ALL_LTC3882-1 OPERATION MFR_RESET PWM Configuration FREQUENCY_SWITCH MFR_PWM_CONFIG_LTC3882-1 MFR_CHAN_CONFIG_LTC3882-1 MFR_PWM_MODE_LTC3882-1 Input Voltage and Limits VIN_ON VIN_OFF VIN_OV_FAULT_LIMIT VIN_UV_WARN_LIMIT Output Voltage and Limits VOUT_MODE VOUT_COMMAND MFR_VOUT_MAX VOUT_MAX MFR_VOUT_AVP VOUT_MARGIN_HIGH VOUT_MARGIN_LOW VOUT_OV_FAULT_LIMIT VOUT_OV_WARN_LIMIT VOUT_UV_WARN_LIMIT VOUT_UV_FAULT_LIMIT Output Current and Limits IOUT_CAL_GAIN MFR_IOUT_CAL_GAIN_TC IOUT_OC_FAULT_LIMIT IOUT_OC_WARN_LIMIT Output Timing, Delays, and Ramping MFR_RESTART_DELAY TON_DELAY TON_RISE TON_MAX_FAULT_LIMIT VOUT_TRANSITION_RATE TOFF_DELAY TOFF_FALL TOFF_MAX_WARN_LIMIT External Temperature and Limits MFR_TEMP_1_GAIN MFR_TEMP_1_OFFSET OT_FAULT_LIMIT OT_WARN_LIMIT Status Reporting STATUS_BYTE UT_FAULT_LIMIT STATUS_WORD STATUS_VOUT STATUS_IOUT STATUS_INPUT STATUS_TEMPERATURE STATUS_CML STATUS_MFR_SPECIFIC MFR_PADS_LTC3882-1 MFR_COMMON MFR_INFO CLEAR_FAULTS Telemetry READ_VIN MFR_VIN_PEAK READ_VOUT MFR_VOUT_PEAK READ_IOUT MFR_IOUT_PEAK READ_POUT READ_TEMPERATURE_1 MFR_TEMPERATURE_1_PEAK READ_TEMPERATURE_2 MFR_TEMPERATURE_2_PEAK READ_DUTY_CYCLE READ_FREQUENCY MFR_CLEAR_PEAKS Fault Response and Communication VIN_OV_FAULT_RESPONSE VOUT_OV_FAULT_RESPONSE VOUT_UV_FAULT_RESPONSE IOUT_OC_FAULT_RESPONSE OT_FAULT_RESPONSE UT_FAULT_RESPONSE MFR_OT_FAULT_RESPONSE TON_MAX_FAULT_RESPONSE MFR_RETRY_DELAY SMBALERT_MASK MFR_FAULT_PROPAGATE_LTC3882-1 MFR_FAULT_RESPONSE MFR_FAULT_LOG Fault Log Operation MFR_FAULT_LOG_CLEAR EEPROM User Access STORE_USER_ALL RESTORE_USER_ALL MFR_COMPARE_USER_ALL MFR_FAULT_LOG_STORE MFR_EE_xxxx USER_DATA_0x Unit Identification MFR_ID MFR_MODEL MFR_SERIAL MFR_SPECIAL_ID Typical Applications Package Description Revision History Typical Application Related Parts
APPLICATIONS INFORMATION
The frequency and phase are also set by EEPROM values. A loop crossover frequency of 100kHz provides good Assume that solution footprint or vertical clearance is an transient performance while still being well below the issue, so operating frequency will need to be increased switching frequency of the converter. The values of R29, in an effort to minimize inductor value (size). This choice R30 and C25 to C27 were determined to produce a nomi- could also result from the need to have above average nal system phase margin of about 65° at this bandwidth. transient performance, although efficiency may be re- For the DCR sense filter network, R = 3.09k and C = 220nF duced slightly. FREQUENCY_SWITCH is set to 1.0MHz. are chosen to match the L/DCR time constant of the induc- As a 2-phase system, MFR_PWM_CONFIG_LTC3882-1 tor. PolyPhase connections (I is programmed to 0x14 to put Channel 0 phase at 0° and AVG, et al) are shown in the schematic to ensure good output current sharing between Channel 1 phase at 180°. This produces the lowest input the two power stages. ripple possible with this configuration and allows this output to synchronize with other rails via SHARE_CLK. External temperature sense will employ an accurate ∆VBE method, and Q1 and Q2 serve to sense the temperature of The design will plan on a nominal output ripple of 70% of L1 and L2, respectively. These components will be located IOUT to minimize the magnetics volume, and the inductance immediately adjacent to their chokes and the 10nF filter value is chosen based on this assumption. Each channel capacitors placed with the BJTs. supplies an average 20A to the output at full load, result- ing in a ripple of 14AP-P. A 200nH inductor per phase Resistor configuration is used on the ASELn pins to pro- would create this peak-to-peak ripple at 1.0MHz. A Pulse gram PMBus address (MFR_ADDRESS) to 0x4C. Each PA0513.22LT 210nH inductor with a DCR of 0.32mΩ LTC3882-1 must be configured for a unique address. typical is selected. Setting IOUT_FAULT_LIMIT to 35A per Using both ASELn pins to accomplish this programming phase leaves plenty of headroom for transient conditions is recommended for simpliest in-system programming. while still adequately protecting against the rated inductor Check the selected address to avoid collision with global saturation current of 45A at temperature. addresses other any other specific devices. Identical MFR_RAIL_ADDRESS can be set in EEPROM for both For top and bottom power FETs, the 40V rated Infineon channels to allow single-command control of common BSC050N04LSG and BSC010N04LS are chosen, respec- rail parameters such as IOUT_OC_FAULT_LIMIT. The tively. These afford both low RDS(ON) and low gate charge LTC3882-1 also responds to 7-bit global addresses 0x5A QG. Two of each of these could be paralleled to achieve and 0x5B. MFR_ADDRESS and MFR_RAIL_ADDRESS improved efficiency at full load, if desired. should not be set to either of these values. The LTC4449 gate driver is chosen for its fast response PMBus connection (three signals), as well as shared (13ns), suitable gate drive, VIN capability (38V) and the RUN control and fault propagation (FAULT) are provided. ease with which it can be interfaced to the LTC3882-1. Basic SYNC can be used to synchronize other PWMs to this three-state control, CCM operation, fast boost refresh, low rail if required. VOUT range and digital output voltage servo are selected by programming MFR_PWM_MODE_LTC3882-1 to 0xC0 Pull-ups are provided on all these shared open-drain signals for both channels. assuming a maximum 100pF line load and PMBus rate of 100kHz. These pins should not be left floating. Termina- For input filtering, a 47μF SUNCON capacitor and four tion to 3.3V ensures the absolute maximum ratings for 22μF ceramic capacitors are selected to provide accept- the pins are not exceeded. All other operating parameters able AC impedance against the designed converter ripple such as soft start/stop and desired faults responses are current. Four 470μF 9mΩ POSCAPs and two 100μF programmed via PMBus command values stored in internal ceramic capacitors are chosen for the output to maintain LTC3882-1 EEPROM. supply regulation during severe transient conditions and to minimize output voltage ripple. Rev B 68 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuit Timing Diagram Operation Overview Main Control Loop Power-Up and Initialization Soft-Start Time-Based Output Sequencing Output Ramping Control Voltage-Based Output Sequencing Minimum Output Disable Times Output Short Cycle Light Load Current Operation Switching Frequency and Phase PolyPhase Load Sharing Active Voltage Positioning Input Supply Monitoring Output Voltage Sensing and Monitoring Output Current Sensing and Monitoring External and Internal Temperature Sense Resistor Configuration Pins Internal EEPROM with CRC and ECC Fault Detection Input Supply Faults Hardwired PWM Response to VOUT Faults Power Good Indication (Master) Power Good Indication (Slave) Hardwired PWM Response to IOUT Faults Hardwired PWM Response to Temperature Faults Hardwired PWM Response to Timing Faults External Faults Fault Handling Status Registers and ALERT Masking FAULT Pin I/O Fault Logging Factory Default Operation Serial Interface Serial Bus Addressing Serial Bus Timeout Serial Communication Errors PMBus Command Summary PMBus Commands Data Formats Applications Information Efficiency Considerations PWM Frequency and Inductor Selection Power MOSFET Selection MOSFET Driver Selection Using PWM Protocols CIN Selection COUT Selection Feedback Loop Compensation PCB Layout Considerations Output Current Sensing Output Voltage Sensing Soft-Start and Stop Time-Based Output Sequencing and Ramping Voltage-Based Output Sequencing Using Output Voltage Servo Using AVP PWM Frequency Synchronization PolyPhase Operation and Load Sharing External Temperature Sense Resistor Configuration Pins Internal Regulator Outputs IC Junction Temperature Derating EEPROM Retention at Temperature Configuring Open-Drain Pins PMBus Communication and Command Processing Status and Fault Log Management LTpowerPlay – An Interactive Digital Power GUI Interfacing to the DC1613 Design Example PMBus COMMAND DETAILS Addressing and Write Protect PAGE PAGE_PLUS_WRITE PAGE_PLUS_READ WRITE_PROTECT MFR_ADDRESS MFR_RAIL_ADDRESS General Device Configuration PMBUS_REVISION CAPABILITY On, Off and Margin Control ON_OFF_CONFIG MFR_CONFIG_ALL_LTC3882-1 OPERATION MFR_RESET PWM Configuration FREQUENCY_SWITCH MFR_PWM_CONFIG_LTC3882-1 MFR_CHAN_CONFIG_LTC3882-1 MFR_PWM_MODE_LTC3882-1 Input Voltage and Limits VIN_ON VIN_OFF VIN_OV_FAULT_LIMIT VIN_UV_WARN_LIMIT Output Voltage and Limits VOUT_MODE VOUT_COMMAND MFR_VOUT_MAX VOUT_MAX MFR_VOUT_AVP VOUT_MARGIN_HIGH VOUT_MARGIN_LOW VOUT_OV_FAULT_LIMIT VOUT_OV_WARN_LIMIT VOUT_UV_WARN_LIMIT VOUT_UV_FAULT_LIMIT Output Current and Limits IOUT_CAL_GAIN MFR_IOUT_CAL_GAIN_TC IOUT_OC_FAULT_LIMIT IOUT_OC_WARN_LIMIT Output Timing, Delays, and Ramping MFR_RESTART_DELAY TON_DELAY TON_RISE TON_MAX_FAULT_LIMIT VOUT_TRANSITION_RATE TOFF_DELAY TOFF_FALL TOFF_MAX_WARN_LIMIT External Temperature and Limits MFR_TEMP_1_GAIN MFR_TEMP_1_OFFSET OT_FAULT_LIMIT OT_WARN_LIMIT Status Reporting STATUS_BYTE UT_FAULT_LIMIT STATUS_WORD STATUS_VOUT STATUS_IOUT STATUS_INPUT STATUS_TEMPERATURE STATUS_CML STATUS_MFR_SPECIFIC MFR_PADS_LTC3882-1 MFR_COMMON MFR_INFO CLEAR_FAULTS Telemetry READ_VIN MFR_VIN_PEAK READ_VOUT MFR_VOUT_PEAK READ_IOUT MFR_IOUT_PEAK READ_POUT READ_TEMPERATURE_1 MFR_TEMPERATURE_1_PEAK READ_TEMPERATURE_2 MFR_TEMPERATURE_2_PEAK READ_DUTY_CYCLE READ_FREQUENCY MFR_CLEAR_PEAKS Fault Response and Communication VIN_OV_FAULT_RESPONSE VOUT_OV_FAULT_RESPONSE VOUT_UV_FAULT_RESPONSE IOUT_OC_FAULT_RESPONSE OT_FAULT_RESPONSE UT_FAULT_RESPONSE MFR_OT_FAULT_RESPONSE TON_MAX_FAULT_RESPONSE MFR_RETRY_DELAY SMBALERT_MASK MFR_FAULT_PROPAGATE_LTC3882-1 MFR_FAULT_RESPONSE MFR_FAULT_LOG Fault Log Operation MFR_FAULT_LOG_CLEAR EEPROM User Access STORE_USER_ALL RESTORE_USER_ALL MFR_COMPARE_USER_ALL MFR_FAULT_LOG_STORE MFR_EE_xxxx USER_DATA_0x Unit Identification MFR_ID MFR_MODEL MFR_SERIAL MFR_SPECIAL_ID Typical Applications Package Description Revision History Typical Application Related Parts
