Datasheet ADP1821 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Step-Down DC-to-DC Controller |
| Pages / Page | 24 / 10 — ADP1821. MOSFET DRIVERS. SETTING THE OUTPUT VOLTAGE. SWITCHING FREQUENCY … |
| Revision | C |
| File Format / Size | PDF / 828 Kb |
| Document Language | English |
ADP1821. MOSFET DRIVERS. SETTING THE OUTPUT VOLTAGE. SWITCHING FREQUENCY CONTROL AND. SYNCHRONIZATION. INPUT VOLTAGE RANGE
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ADP1821 MOSFET DRIVERS SETTING THE OUTPUT VOLTAGE
The DH pin drives the high-side switch MOSFET. This is a The output voltage is set using a resistive voltage divider from boosted 5 V gate driver that is powered by a bootstrap capacitor the output to FB. The voltage divider drops the output voltage circuit. This configuration allows the high-side, N-channel to the 0.6 V FB regulation voltage to set the regulation output MOSFET gate to be driven above the input voltage, allowing full voltage. The output voltage is set to voltages as low as 0.6 V and enhancement and a low voltage drop across the MOSFET. The as high as 85% of the minimum power input voltage (see the bootstrap capacitor is connected from the SW pin to the BST Feedback Voltage Divider section). pin. A bootstrap Schottky diode connected from the PVCC pin to the BST pin recharges the bootstrap capacitor every time the
SWITCHING FREQUENCY CONTROL AND
SW node goes low. Use a bootstrap capacitor value greater than
SYNCHRONIZATION
100× the high-side MOSFET input capacitance. The ADP1821 has a logic-controlled frequency select input (FREQ) In practice, the switch node can run up to 24 V of input voltage, which sets the switching frequency to 300 kHz or 600 kHz. Drive and the boost nodes can operate more than 5 V above this to FREQ low for 300 kHz and high for 600 kHz. allow full gate drive. The power input voltage can be run from The SYNC input is used to synchronize the converter switching 1 V to 24 V. frequency to an external signal. The converter switching can be The switching cycle is initiated by the internal clock signal. The synchronized to an external signal. This allows multiple ADP1821 high-side MOSFET is turned on by the DH driver, and the SW converters to be operated at the same frequency to prevent node goes high, pulling up on the inductor. When the internally frequency beating or other interactions. generated ramp signal crosses the COMP pin voltage, the switch To synchronize the ADP1821 switching to an external signal, MOSFET is turned off and the low-side synchronous rectifier drive the SYNC input with a synchronizing signal. The ADP1821 MOSFET is turned on by the DL driver. Active break-before- can only synchronize up to 2× the nominal oscillator frequency. make circuitry as well as a supplemental fixed dead time are If the frequency is set to 300 kHz (FREQ connected to GND), used to prevent cross-conduction in the switches. then the synchronization frequency needs to be in between The DL pin provides the gate drive for the low-side MOSFET 300 kHz and 600 kHz. Since the 300 kHz setting has a mini- synchronous rectifier. Internal circuitry monitors the external mum specification (see Table 1) of 250 kHz and a maximum MOSFETs to ensure break-before-make switching to prevent of 375 kHz over the specified temperature range, the recom- cross-conduction. An active dead-time reduction circuit mended synchronization frequency range is between 375 kHz reduces the break-before-make time of the switching to limit and 500 kHz to cover the whole range of part-to-part variation the losses due to current flowing through the synchronous and over the operating temperature range. If the frequency is set rectifier body diode. to 600 kHz (FREQ connected to VCC), then the synchronization frequency needs to be in between 600 kHz and 1.2 MHz. Since The PVCC pin provides power to the low-side drivers. It is the 600 kHz setting has a minimum specification (see Table 1) limited to 5.5 V maximum input and should have a local of 470 kHz and a maximum of 720 kHz over the specified tem- decoupling capacitor to PGND. perature range, the recommended synchronization frequency The synchronous rectifier is turned on for a minimum time range is between 720 kHz and 940 kHz to cover the whole range of about 200 ns on every switching cycle in order to sense the of part-to-part variation and over the operating temperature current. This and the nonoverlap dead time put a limit on the range. Driving SYNC faster than recommended for the FREQ maximum high-side switch duty cycle based on the selected setting results in a small ramp signal, which could affect the switching frequency. Typically, this is about 90% at 300 kHz signal-to-noise ratio and the modulator gain and stability. switching, and at 1 MHz switching, it reduces to about 70% When an external clock is detected at the first SYNC edge, maximum duty cycle. the internal oscillator is reset and clock control shifts to SYNC.
INPUT VOLTAGE RANGE
The SYNC edges then trigger subsequent clocking of the PWM The ADP1821 takes its internal power from the VCC and PVCC outputs. The DH rising edges appear about 320 ns after the cor- inputs. PVCC powers the low-side MOSFET gate drive (DL), responding SYNC edge, and the frequency is locked to the and VCC powers the internal control circuitry. Both of these external signal. If the external SYNC signal disappears during inputs are limited to between 3.7 V and 5.5 V. Bypass PVCC to operation, the ADP1821 reverts to its internal oscillator and PGND with a 1 μF or greater capacitor. Bypass VCC to GND experiences a delay of no more than a single cycle of the with a 0.1 μF or greater capacitor. internal oscillator. The power input to the dc-to-dc converter can range between 1.2× the output voltage and 24 V. Bypass the power input to PGND with a suitably large capacitor. See the Selecting the Input Capacitor section. Rev. C | Page 10 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION SIMPLIFIED BLOCK DIAGRAM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SOFT START ERROR AMPLIFIER CURRENT-LIMIT SCHEME MOSFET DRIVERS INPUT VOLTAGE RANGE SETTING THE OUTPUT VOLTAGE SWITCHING FREQUENCY CONTROL AND SYNCHRONIZATION COMPENSATION POWER-GOOD INDICATOR THERMAL SHUTDOWN SHUTDOWN CONTROL APPLICATION INFORMATION SELECTING THE INPUT CAPACITOR OUTPUT LC FILTER SELECTING THE MOSFETS SETTING THE CURRENT LIMIT FEEDBACK VOLTAGE DIVIDER COMPENSATING THE VOLTAGE MODE BUCK REGULATOR Type II Compensator Type III Compensator SETTING THE SOFT START PERIOD PCB LAYOUT GUIDELINE RECOMMENDED COMPONENT MANUFACTURERS APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
ADP1821 MOSFET DRIVERS SETTING THE OUTPUT VOLTAGE
The DH pin drives the high-side switch MOSFET. This is a The output voltage is set using a resistive voltage divider from boosted 5 V gate driver that is powered by a bootstrap capacitor the output to FB. The voltage divider drops the output voltage circuit. This configuration allows the high-side, N-channel to the 0.6 V FB regulation voltage to set the regulation output MOSFET gate to be driven above the input voltage, allowing full voltage. The output voltage is set to voltages as low as 0.6 V and enhancement and a low voltage drop across the MOSFET. The as high as 85% of the minimum power input voltage (see the bootstrap capacitor is connected from the SW pin to the BST Feedback Voltage Divider section). pin. A bootstrap Schottky diode connected from the PVCC pin to the BST pin recharges the bootstrap capacitor every time the
SWITCHING FREQUENCY CONTROL AND
SW node goes low. Use a bootstrap capacitor value greater than
SYNCHRONIZATION
100× the high-side MOSFET input capacitance. The ADP1821 has a logic-controlled frequency select input (FREQ) In practice, the switch node can run up to 24 V of input voltage, which sets the switching frequency to 300 kHz or 600 kHz. Drive and the boost nodes can operate more than 5 V above this to FREQ low for 300 kHz and high for 600 kHz. allow full gate drive. The power input voltage can be run from The SYNC input is used to synchronize the converter switching 1 V to 24 V. frequency to an external signal. The converter switching can be The switching cycle is initiated by the internal clock signal. The synchronized to an external signal. This allows multiple ADP1821 high-side MOSFET is turned on by the DH driver, and the SW converters to be operated at the same frequency to prevent node goes high, pulling up on the inductor. When the internally frequency beating or other interactions. generated ramp signal crosses the COMP pin voltage, the switch To synchronize the ADP1821 switching to an external signal, MOSFET is turned off and the low-side synchronous rectifier drive the SYNC input with a synchronizing signal. The ADP1821 MOSFET is turned on by the DL driver. Active break-before- can only synchronize up to 2× the nominal oscillator frequency. make circuitry as well as a supplemental fixed dead time are If the frequency is set to 300 kHz (FREQ connected to GND), used to prevent cross-conduction in the switches. then the synchronization frequency needs to be in between The DL pin provides the gate drive for the low-side MOSFET 300 kHz and 600 kHz. Since the 300 kHz setting has a mini- synchronous rectifier. Internal circuitry monitors the external mum specification (see Table 1) of 250 kHz and a maximum MOSFETs to ensure break-before-make switching to prevent of 375 kHz over the specified temperature range, the recom- cross-conduction. An active dead-time reduction circuit mended synchronization frequency range is between 375 kHz reduces the break-before-make time of the switching to limit and 500 kHz to cover the whole range of part-to-part variation the losses due to current flowing through the synchronous and over the operating temperature range. If the frequency is set rectifier body diode. to 600 kHz (FREQ connected to VCC), then the synchronization frequency needs to be in between 600 kHz and 1.2 MHz. Since The PVCC pin provides power to the low-side drivers. It is the 600 kHz setting has a minimum specification (see Table 1) limited to 5.5 V maximum input and should have a local of 470 kHz and a maximum of 720 kHz over the specified tem- decoupling capacitor to PGND. perature range, the recommended synchronization frequency The synchronous rectifier is turned on for a minimum time range is between 720 kHz and 940 kHz to cover the whole range of about 200 ns on every switching cycle in order to sense the of part-to-part variation and over the operating temperature current. This and the nonoverlap dead time put a limit on the range. Driving SYNC faster than recommended for the FREQ maximum high-side switch duty cycle based on the selected setting results in a small ramp signal, which could affect the switching frequency. Typically, this is about 90% at 300 kHz signal-to-noise ratio and the modulator gain and stability. switching, and at 1 MHz switching, it reduces to about 70% When an external clock is detected at the first SYNC edge, maximum duty cycle. the internal oscillator is reset and clock control shifts to SYNC.
INPUT VOLTAGE RANGE
The SYNC edges then trigger subsequent clocking of the PWM The ADP1821 takes its internal power from the VCC and PVCC outputs. The DH rising edges appear about 320 ns after the cor- inputs. PVCC powers the low-side MOSFET gate drive (DL), responding SYNC edge, and the frequency is locked to the and VCC powers the internal control circuitry. Both of these external signal. If the external SYNC signal disappears during inputs are limited to between 3.7 V and 5.5 V. Bypass PVCC to operation, the ADP1821 reverts to its internal oscillator and PGND with a 1 μF or greater capacitor. Bypass VCC to GND experiences a delay of no more than a single cycle of the with a 0.1 μF or greater capacitor. internal oscillator. The power input to the dc-to-dc converter can range between 1.2× the output voltage and 24 V. Bypass the power input to PGND with a suitably large capacitor. See the Selecting the Input Capacitor section. Rev. C | Page 10 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION SIMPLIFIED BLOCK DIAGRAM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SOFT START ERROR AMPLIFIER CURRENT-LIMIT SCHEME MOSFET DRIVERS INPUT VOLTAGE RANGE SETTING THE OUTPUT VOLTAGE SWITCHING FREQUENCY CONTROL AND SYNCHRONIZATION COMPENSATION POWER-GOOD INDICATOR THERMAL SHUTDOWN SHUTDOWN CONTROL APPLICATION INFORMATION SELECTING THE INPUT CAPACITOR OUTPUT LC FILTER SELECTING THE MOSFETS SETTING THE CURRENT LIMIT FEEDBACK VOLTAGE DIVIDER COMPENSATING THE VOLTAGE MODE BUCK REGULATOR Type II Compensator Type III Compensator SETTING THE SOFT START PERIOD PCB LAYOUT GUIDELINE RECOMMENDED COMPONENT MANUFACTURERS APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
