Datasheet ADP1821 (Analog Devices) - 3

ADP1821 SPECIFICATIONS
VVCC = VPVCC = V = V SHDN FREQ = 5 V, SYNC = GND. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA=25°C.
Table 1. Parameter Conditions Min Typ Max Unit
POWER SUPPLY Input Voltage 3.7 5.5 V Undervoltage Lockout Threshold VVCC rising, TJ = −40°C to +125°C 2.4 2.7 3.0 V Undervoltage Lockout Threshold VVCC rising, TA = 25°C 2.5 2.7 2.9 V Undervoltage Lockout Hysteresis VVCC 0.1 V Quiescent Current IVCC + IVCC, not switching 1 2 mA Shutdown Current SHDN = GND 10 μA Power Stage Supply Voltage 1.0 24 V ERROR AMPLIFIER FB Regulation Voltage TJ = −40°C to +85°C 594 600 606 mV FB Regulation Voltage TJ = −40°C to +125°C 588 600 606 mV FB Input Bias Current −100 +1 +100 nA Error Amplifier Open-Loop Voltage Gain 70 dB COMP Output Sink Current 600 μA COMP Output Source Current 110 μA COMP Clamp High Voltage 2.4 V COMP Clamp Low Voltage 0.75 V PWM CONTROLLER PWM Peak Ramp Voltage 1.25 V DL Minimum On Time FREQ = VCC (300 kHz) 120 170 220 ns DL Minimum On-Time FREQ = VCC (300 kHz), TA = 25°C 140 170 200 ns DH Maximum Duty Cycle FREQ = GND (300 kHz) 85 90 % DH Minimum Duty Cycle FREQ = GND (300 kHz) 1 3 % SOFT START SS Pull-Up Resistance SS = GND 95 kΩ SS Pull-Down Resistance VSS = 0.6 V 1.65 2.5 4.2 kΩ OSCILLATOR Oscillator Frequency FREQ = GND 250 310 375 kHz FREQ = VCC 470 570 720 kHz Synchronization Range FREQ = GND 300 600 kHz FREQ = VCC 600 1200 kHz SYNC Minimum Pulse Width 80 ns CURRENT SENSE CSL Threshold Voltage Relative to PGND −30 0 +30 mV CSL Output Current VCSL = 0 V 42 50 54 μA Current Sense Blanking Period 160 ns GATE DRIVERS DH Rise Time CGATE = 3 nF, VDH = VIN, VBST − VSW = 5 V 16 ns DH Fall Time CGATE = 3 nF, VDH = VIN, VBST − VSW = 5 V 12 ns DL Rise Time CGATE = 3 nF, VDL = VIN 19 ns DL Fall Time CGATE = 3 nF, VDL = 0 V 13 ns DL Low to DH High Dead Time 33 ns DH Low to DL High Dead Time 42 ns Rev. C | Page 3 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION SIMPLIFIED BLOCK DIAGRAM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SOFT START ERROR AMPLIFIER CURRENT-LIMIT SCHEME MOSFET DRIVERS INPUT VOLTAGE RANGE SETTING THE OUTPUT VOLTAGE SWITCHING FREQUENCY CONTROL AND SYNCHRONIZATION COMPENSATION POWER-GOOD INDICATOR THERMAL SHUTDOWN SHUTDOWN CONTROL APPLICATION INFORMATION SELECTING THE INPUT CAPACITOR OUTPUT LC FILTER SELECTING THE MOSFETS SETTING THE CURRENT LIMIT FEEDBACK VOLTAGE DIVIDER COMPENSATING THE VOLTAGE MODE BUCK REGULATOR Type II Compensator Type III Compensator SETTING THE SOFT START PERIOD PCB LAYOUT GUIDELINE RECOMMENDED COMPONENT MANUFACTURERS APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE