Datasheet MASTERGAN2 (STMicroelectronics) - 4
| Manufacturer | STMicroelectronics |
| Description | High power density 600V Half bridge driver with two enhancement mode GaN HEMT |
| Pages / Page | 29 / 4 — MASTERGAN2. Electrical Data. 3.1. Absolute maximum ratings. Table 2. … |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
MASTERGAN2. Electrical Data. 3.1. Absolute maximum ratings. Table 2. Absolute maximum ratings. Symbol. Parameter. Test Condition. Value
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MASTERGAN2 Electrical Data 3 Electrical Data 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings
each voltage referred to GND unless otherwise specified
Symbol Parameter Test Condition Value Unit
VDS GaN Drain-to-Source Voltage TJ = 25 °C 620 V VCC Logic supply voltage -0.3 to 11 V PVCC-PGND Low-side driver supply voltage (1) -0.3 to 7 V VCC-PGND Logic supply vs. Low-side driver ground -0.3 to 18.3 V PVCC Low-side driver supply vs. logic ground -0.3 to 18.3 V PGND Low-side driver ground vs. logic ground -7.3 to 11.3 V VBO BOOT to OUTb voltage (2) -0.3 to 7 V BOOT Bootstrap voltage -0.3 to 620 V Maximum external capacitance between GL and PGND and CGL, CGH F between GH and OUTb sw = 500 MHz (3) 3.9 nF Minimum external pull-down resistance between GL and RGL, RGH 6.8 kΩ PGND and GH and OUTb DC @ TCB = 25°C (4) (5) 9.7 A ID Drain current (Low side GaN transistor) DC @ TCB = 100°C(4) (5) 6.4 A Peak @ TCB = 25°C(4) (5) (6) 17 A DC @ TCB = 25°C (4) (5) 6.5 A ID Drain current (High side GaN transistor) DC @ TCB = 100°C(4) (5) 4.4 A Peak @ TCB = 25°C(4) (5) (6) 12 A SRout Half-bridge outputs slew rate (10% - 90%) 100 V/ns Vi Logic inputs voltage range -0.3 to 21 V TJ Junction temperature -40 to 150 °C Ts Storage temperature -40 to 150 °C 1. PGND internally connected to SENSE 2. OUTb internally connected to OUT 3. CGx < 0.08/(Pvcc^2*Fsw)-(330*10-12) 4. TCB is temperature of case exposed pad. 5. Range estimated by characterization, not tested in production. 6. Value specified by design factor, pulse duration limited to 50 µs and junction temperature.
DS13597
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Rev 1 page 4/29
Document Outline Features Application Description 1 Block diagram 2 Pin description and connection diagram 2.1 Pin list 3 Electrical Data 3.1 Absolute maximum ratings 3.2 Recommended operating conditions 3.3 Thermal data 4 Electrical characteristics 4.1 Driver 4.2 GaN power transistor 5 Device characterization values 6 Functional description 6.1 Logic inputs 6.2 Bootstrap structure 6.3 VCC supply pins and UVLO function 6.4 VBO UVLO protection 6.5 Thermal shutdown 7 Typical application diagrams 8 Package information 8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information 9 Suggested footprint 10 Ordering information Revision history Contents List of tables List of figures
MASTERGAN2 Electrical Data 3 Electrical Data 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings
each voltage referred to GND unless otherwise specified
Symbol Parameter Test Condition Value Unit
VDS GaN Drain-to-Source Voltage TJ = 25 °C 620 V VCC Logic supply voltage -0.3 to 11 V PVCC-PGND Low-side driver supply voltage (1) -0.3 to 7 V VCC-PGND Logic supply vs. Low-side driver ground -0.3 to 18.3 V PVCC Low-side driver supply vs. logic ground -0.3 to 18.3 V PGND Low-side driver ground vs. logic ground -7.3 to 11.3 V VBO BOOT to OUTb voltage (2) -0.3 to 7 V BOOT Bootstrap voltage -0.3 to 620 V Maximum external capacitance between GL and PGND and CGL, CGH F between GH and OUTb sw = 500 MHz (3) 3.9 nF Minimum external pull-down resistance between GL and RGL, RGH 6.8 kΩ PGND and GH and OUTb DC @ TCB = 25°C (4) (5) 9.7 A ID Drain current (Low side GaN transistor) DC @ TCB = 100°C(4) (5) 6.4 A Peak @ TCB = 25°C(4) (5) (6) 17 A DC @ TCB = 25°C (4) (5) 6.5 A ID Drain current (High side GaN transistor) DC @ TCB = 100°C(4) (5) 4.4 A Peak @ TCB = 25°C(4) (5) (6) 12 A SRout Half-bridge outputs slew rate (10% - 90%) 100 V/ns Vi Logic inputs voltage range -0.3 to 21 V TJ Junction temperature -40 to 150 °C Ts Storage temperature -40 to 150 °C 1. PGND internally connected to SENSE 2. OUTb internally connected to OUT 3. CGx < 0.08/(Pvcc^2*Fsw)-(330*10-12) 4. TCB is temperature of case exposed pad. 5. Range estimated by characterization, not tested in production. 6. Value specified by design factor, pulse duration limited to 50 µs and junction temperature.
DS13597
-
Rev 1 page 4/29
Document Outline Features Application Description 1 Block diagram 2 Pin description and connection diagram 2.1 Pin list 3 Electrical Data 3.1 Absolute maximum ratings 3.2 Recommended operating conditions 3.3 Thermal data 4 Electrical characteristics 4.1 Driver 4.2 GaN power transistor 5 Device characterization values 6 Functional description 6.1 Logic inputs 6.2 Bootstrap structure 6.3 VCC supply pins and UVLO function 6.4 VBO UVLO protection 6.5 Thermal shutdown 7 Typical application diagrams 8 Package information 8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information 9 Suggested footprint 10 Ordering information Revision history Contents List of tables List of figures
