Datasheet ADL9005 (Analog Devices) - 7

Data Sheet ADL9005 INTERFACE SCHEMATICS RBIAS RFIN ACG2 ACG1
003 005 25033- 25033- Figure 3. RBIAS Interface Schematic Figure 5. RFIN, ACG1, and ACG2 Interface Schematic
RFOUT/VDD ACG4/VDD2 GND ACG3
004 006 25033- 25033- Figure 4. GND Interface Schematic Figure 6. RFOUT/VDD, ACG3, and ACG4/VDD2 Interface Schematic Rev. 0 | Page 7 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 0.01 GHz TO 14 GHz 14 GHz TO 20 GHz 20 GHz TO 26.5 GHz DC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ELECTROSTATIC DISCHARGE (ESD) RATINGS ESD Ratings for ADL9005 ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS BIASING THROUGH THE ACG4/VDD2 PIN THEORY OF OPERATION APPLICATIONS INFORMATION BASIC CONNECTIONS BIASING THE ADL9005 BY USING THE LTM8020 PROVIDING DRAIN BIAS PROVIDING DRAIN BIAS THROUGH THE ACG4/VDD2 PIN POWER-UP AND POWER-DOWN SEQUENCING OUTLINE DIMENSIONS ORDERING GUIDE