Datasheet HMC902LP3E (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 5 GHz to 11 GHz GaAs, pHEMT, MMIC, Low Noise Amplifier |
| Pages / Page | 13 / 5 — Data Sheet. HMC902LP3E. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. NIC. … |
| Revision | E |
| File Format / Size | PDF / 413 Kb |
| Document Language | English |
Data Sheet. HMC902LP3E. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. NIC. TOP VIEW. (Not to Scale). RFOUT. GND. PACKAGE. BASE
Model Line for this Datasheet
Text Version of Document
link to page 5 link to page 5 link to page 12 link to page 5 link to page 5 link to page 12 link to page 12 link to page 5
Data Sheet HMC902LP3E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 C C DD DD NI V V NI 6 5 4 3 1 1 1 1 NIC 1 12 NIC NIC 2 HMC902LP3E 11 NIC TOP VIEW RF 3 (Not to Scale) 10 IN RFOUT GND 4 9 GND 5 6 7 8 C 1 2 C PACKAGE NI GG GG NI BASE V V GND NOTES 1. NIC = NOT INTERNALLY CONNECTED. HOWEVER, ALL DATA SHOWN IN THIS DATA SHEET IS MEASURED WITH THESE PINS CONNECTED TO RF/DC GROUND EXTERNALLY.
2
2. EXPOSED PAD. THE PACKAGE BOTTOM HAS AN EXPOSED
-00
METAL GROUND PADDLE THAT MUST BE CONNECTED TO
524
RF/DC GROUND.
14 Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1, 2, 5, 8, 11 to NIC Not Internally Connected. However, all data shown in this data sheet is measured with these pins 13, 16 connected to RF/dc ground externally. 3 RFIN RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic. 4, 9 GND Ground. Connect these pins to RF/dc ground. See Figure 4 for the interface schematic. 6, 7 VGG1, VGG2 Optional Gate Control for Amplifier. If left open, the amplifier runs self biased at the standard current. Applying a negative voltage reduces drain current. External capacitors are required (see Figure 24). See Figure 5 for the interface schematic. 10 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. 14, 15 VDD2, VDD1 Power Supply Voltage for the Amplifier. See Figure 23 and Figure 24 for the application circuits. See Figure 7 for the interface schematic. EPAD Exposed Pad. The package bottom has an exposed metal ground paddle that must be connected to RF/dc ground.
INTERFACE SCHEMATICS RF RF IN OUT
6 03 0 -00 4 4- 52 452 14 1 Figure 3. RFIN Interface Schematic Figure 6. RFOUT Interface Schematic
GND V
04
DD1,
0 4-
VDD2
52 07 14 0 24- 145 Figure 4. GND Interface Schematic Figure 7. VDD1 and VDD2 Interface Schematic -005
VGG1, VGG2
4524 1 Figure 5. VGG1 and VGG2 Interface Schematic Rev. E | Page 5 of 13 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD (PCB) APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet HMC902LP3E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 C C DD DD NI V V NI 6 5 4 3 1 1 1 1 NIC 1 12 NIC NIC 2 HMC902LP3E 11 NIC TOP VIEW RF 3 (Not to Scale) 10 IN RFOUT GND 4 9 GND 5 6 7 8 C 1 2 C PACKAGE NI GG GG NI BASE V V GND NOTES 1. NIC = NOT INTERNALLY CONNECTED. HOWEVER, ALL DATA SHOWN IN THIS DATA SHEET IS MEASURED WITH THESE PINS CONNECTED TO RF/DC GROUND EXTERNALLY.
2
2. EXPOSED PAD. THE PACKAGE BOTTOM HAS AN EXPOSED
-00
METAL GROUND PADDLE THAT MUST BE CONNECTED TO
524
RF/DC GROUND.
14 Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1, 2, 5, 8, 11 to NIC Not Internally Connected. However, all data shown in this data sheet is measured with these pins 13, 16 connected to RF/dc ground externally. 3 RFIN RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic. 4, 9 GND Ground. Connect these pins to RF/dc ground. See Figure 4 for the interface schematic. 6, 7 VGG1, VGG2 Optional Gate Control for Amplifier. If left open, the amplifier runs self biased at the standard current. Applying a negative voltage reduces drain current. External capacitors are required (see Figure 24). See Figure 5 for the interface schematic. 10 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. 14, 15 VDD2, VDD1 Power Supply Voltage for the Amplifier. See Figure 23 and Figure 24 for the application circuits. See Figure 7 for the interface schematic. EPAD Exposed Pad. The package bottom has an exposed metal ground paddle that must be connected to RF/dc ground.
INTERFACE SCHEMATICS RF RF IN OUT
6 03 0 -00 4 4- 52 452 14 1 Figure 3. RFIN Interface Schematic Figure 6. RFOUT Interface Schematic
GND V
04
DD1,
0 4-
VDD2
52 07 14 0 24- 145 Figure 4. GND Interface Schematic Figure 7. VDD1 and VDD2 Interface Schematic -005
VGG1, VGG2
4524 1 Figure 5. VGG1 and VGG2 Interface Schematic Rev. E | Page 5 of 13 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD (PCB) APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
