Datasheet ADRF5547 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Dual-Channel, 3.7 GHz to 5.3 GHz, Receiver Front End |
| Pages / Page | 15 / 5 — Data Sheet. ADRF5547. ABSOLUTE MAXIMUM RATINGS. THERMAL RESISTANCE. Table … |
| Revision | A |
| File Format / Size | PDF / 321 Kb |
| Document Language | English |
Data Sheet. ADRF5547. ABSOLUTE MAXIMUM RATINGS. THERMAL RESISTANCE. Table 2. Parameter. Rating. Table 3. Thermal Resistance
Model Line for this Datasheet
Text Version of Document
Data Sheet ADRF5547 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Rating
Thermal performance is directly linked to printed circuit board Positive Supply Voltage (PCB) design and operation environment. Careful attention to VDD1-ChA, VDD1-ChB, VDD2-ChA, 7 V PCB thermal design is required. VDD2-ChB θJC is the junction to case bottom (channel to package bottom) SWVDD-ChAB 5.4 V thermal resistance. Digital Control Input Voltage SWCTRL-ChAB −0.3 V to V 1
Table 3. Thermal Resistance
DD + 0.3 V BP-ChA, BP-ChB, PD-ChAB −0.3 V to V 1
Package Type θJC Unit
DD + 0.3 V CP-40-15 RF Input Power (LTE Peak) High Gain and Low Gain Mode 30 °C/W Transmit 53 dBm Power-Down Mode 8.7 °C/W Receive 25 dBm Temperature Storage −65°C to +150°C
ESD CAUTION
Reflow (Moisture Sensitivity Level (MSL) 3 260°C Rating) Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) 1 kV, Class 1C Charge Device Model (CDM) 1.25 kV 1 VDD is the voltage of the VDD1-ChA, VDD1-ChB, VDD2-ChA, and VDD2-ChB pins. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 5 of 15 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVE OPERATION, HIGH GAIN MODE RECEIVE OPERATION, LOW GAIN MODE TRANSMIT OPERATION THEORY OF OPERATION SIGNAL PATH SELECT Receive Operation BIASING SEQUENCE APPLICATIONS INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
Thermal performance is directly linked to printed circuit board Positive Supply Voltage (PCB) design and operation environment. Careful attention to VDD1-ChA, VDD1-ChB, VDD2-ChA, 7 V PCB thermal design is required. VDD2-ChB θJC is the junction to case bottom (channel to package bottom) SWVDD-ChAB 5.4 V thermal resistance. Digital Control Input Voltage SWCTRL-ChAB −0.3 V to V 1
Table 3. Thermal Resistance
DD + 0.3 V BP-ChA, BP-ChB, PD-ChAB −0.3 V to V 1
Package Type θJC Unit
DD + 0.3 V CP-40-15 RF Input Power (LTE Peak) High Gain and Low Gain Mode 30 °C/W Transmit 53 dBm Power-Down Mode 8.7 °C/W Receive 25 dBm Temperature Storage −65°C to +150°C
ESD CAUTION
Reflow (Moisture Sensitivity Level (MSL) 3 260°C Rating) Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) 1 kV, Class 1C Charge Device Model (CDM) 1.25 kV 1 VDD is the voltage of the VDD1-ChA, VDD1-ChB, VDD2-ChA, and VDD2-ChB pins. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 5 of 15 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVE OPERATION, HIGH GAIN MODE RECEIVE OPERATION, LOW GAIN MODE TRANSMIT OPERATION THEORY OF OPERATION SIGNAL PATH SELECT Receive Operation BIASING SEQUENCE APPLICATIONS INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
