Datasheet ADRF5547 (Analog Devices) - 6

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ADRF5547 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A A h A Ch Ch M-C C C ND ER ND ND ND DD1- C DD2- G T NI G G G V NI NI V 40 39 38 37 36 35 34 33 32 31 GND 1 30 GND GND 2 29 RxOUT-ChA ANT-ChA 3 28 GND GND 4 27 BP-ChA SWCTRL-ChAB 5 ADRF5547 26 PD-ChAB SWVDD-ChAB 6 TOP VIEW 25 NIC GND 7 (Not to Scale) 24 BP-ChB ANT-ChB 8 23 GND GND 9 22 RxOUT-ChB GND 10 21 GND 11 12 13 14 15 16 17 18 19 20 B C B C C B ND h NI ND ND ND NI NI G G G G Ch Ch M-C ER DD1- DD2- T V V NOTES 1. NIC = NOT INTERNALLY CONNECTED. IT IS RECOMMENDED TO CONNECT NIC TO THE RF GROUND OF THE PCB.
002
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF OR DC GROUND.
20790- Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1, 2, 4, 7, 9 to 11, 14 to 16, 21, 23, 28, 30, 35 to 37, 40 GND Ground. See Figure 3 for the interface schematic. 3 ANT-ChA RF Input to Channel A. 5 SWCTRL-ChAB Control Voltage for Switches on Channel A and Channel B. See Figure 7 for the interface schematic. 6 SWVDD-ChAB Supply Voltage for Switches on Channel A and Channel B. See Figure 7 for the interface schematic. 8 ANT-ChB RF Input to Channel B. 12 TERM-ChB Termination Output. This pin is the transmitter path for Channel B. 13, 18, 19, 25, 32, 33, 38 NIC Not Internally Connected. It is recommended to connect NIC to the RF ground of the PCB. 17 VDD1-ChB Supply Voltage for Stage 1 LNA on Channel B. See Figure 5 for the interface schematic. 20 VDD2-ChB Supply Voltage for Stage 2 LNA on Channel B. See Figure 5 for the interface schematic. 22 RxOUT-ChB RF Output. This pin is the receiver path for Channel B. See Figure 4 for the interface schematic. 24 BP-ChB Bypass Second Stage LNA of Channel B. See Figure 6 for the interface schematic. 26 PD-ChAB Power-Down All Stages of LNA for Channel A and Channel B. See Figure 6 for the Interface schematic. 27 BP-ChA Bypass Second Stage LNA of Channel A. See Figure 6 for the interface schematic. 29 RxOUT-ChA RF Output. This pin is the receiver path for Channel A. See Figure 4 for the interface schematic. 31 VDD2-ChA Supply Voltage for Stage 2 LNA on Channel A. See Figure 5 for the interface schematic. 34 VDD1-ChA Supply Voltage for Stage 1 LNA on Channel A. See Figure 5 for the interface schematic. 39 TERM-ChA Termination Output. This pin is the transmitter path for Channel A. EPAD Exposed Pad. The exposed pad must be connected to RF or dc ground. Rev. A | Page 6 of 15 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVE OPERATION, HIGH GAIN MODE RECEIVE OPERATION, LOW GAIN MODE TRANSMIT OPERATION THEORY OF OPERATION SIGNAL PATH SELECT Receive Operation BIASING SEQUENCE APPLICATIONS INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE