Data SheetAD8324060V–10CH PWR12dBmOUT = 57dBmV/TONEWORST ACP –61dBc50@ MAX GAIN–2040–3030)–40)20m B–50(d10T(dBmVOU–600POUTV–70–10–80–20CU1CU1–90C0C0 -013 0 –30 39- CL1CL1–100 043 –40 04339-0-016 CENTER 21 MHz100 kHz/DIVSPAN 1 MHz41.641.741.841.942.042.142.242.342.442.5FREQUENCY (MHz) Figure 13. Adjacent Channel Power Figure 16. Two-Tone Intermodulation Distortion 400TXEN = 0–10V30IN = 27.5dBmVDEC60–2020DEC54–30DEC48)10B)DEC42d –40B(d (0DEC36ION –50INTDEC30AGAL –60–10ODEC24ISDEC18–70–20DEC12–80MAX GAIN–30DEC 1 TO DEC 6 14 17 0 –90 0 -0- 0- MIN GAIN 9- 339 –40 433 04 –100 0 0.111010010001101001000FREQUENCY (MHz)FREQUENCY (MHz) Figure 14. AC Response Figure 17. Isolation in Transmit Disable Mode vs. Frequency 1.42.0f = 10MHz1.31.5) 1.21.0B d1.10.5f = 5MHz1.0ROR (dB)0Rf = 10MHzSTEP SIZE ( T 0.9–0.5f = 42MHzTPUGAIN EOU 0.8–1.0f = 65MHz0.7–1.50.6 04339-0-015 –2.0 04339-0-018 0612182430364248546006121824303642485460GAIN CONTROL (Decimal Code)GAIN CONTROL (Decimal Code) Figure 15. Output Step Size vs. Gain Control Figure 18. Gain Error vs. Gain Control for Various Frequencies Rev. C | Page 9 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE