Datasheet AD8325 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 5 V CATV Line Driver Fine Step Output Power Control |
| Pages / Page | 16 / 4 — AD8325. ABSOLUTE MAXIMUM RATINGS*. PIN CONFIGURATION. DATEN. 28 GND. … |
| Revision | A |
| File Format / Size | PDF / 749 Kb |
| Document Language | English |
AD8325. ABSOLUTE MAXIMUM RATINGS*. PIN CONFIGURATION. DATEN. 28 GND. SDATA 2. 27 VCC. CLK 3. 26 VIN–. GND 4. 25 VIN+. 24 GND. TXEN 6. 23 V. SLEEP
Model Line for this Datasheet
Text Version of Document
AD8325 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
Supply Voltage +VS Pins 5, 9, 10, 19, 20, 23, 27 . 6 V
DATEN 1 28 GND
Input Voltages
SDATA 2 27 VCC
Pins 25, 26 . ± 0.5 V
CLK 3 26 VIN–
Pins 1, 2, 3, 6, 7 . –0.8 V to +5.5 V
GND 4 25 VIN+
Internal Power Dissipation
V 5 24 GND CC
TSSOP . 0.9 W
TXEN 6 23 V AD8325 CC
Operating Temperature Range . –40∞C to +85∞C
SLEEP 7 TOP VIEW 22 GND
Storage Temperature Range . –65∞C to +150∞C
(Not to Scale) GND 8 21 BYP
Lead Temperature, Soldering 60 seconds . 300∞C
V 9 20 CC VCC
*Stresses above those listed under Absolute Maximum Ratings may cause perma
V 10 19 CC VCC
nent damage to the device. This is a stress rating only; functional operation of the
GND 11 18 GND
device at these or any other conditions above those indicated in the operational
GND 12 17 GND
section of this specification is not implied. Exposure to absolute maximum rating
GND 13 16 GND
conditions for extended periods may affect device reliability.
OUT– 14 15 OUT+ ORDERING GUIDE Model Temperature Range Package Description
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JA Package Option
AD8325ARU –40∞C to +85∞C 28-Lead TSSOP 67.7∞C/W1 RU-28 AD8325ARU-REEL –40∞C to +85∞C 28-Lead TSSOP 67.7∞C/W1 RU-28 AD8325ARUZ2 –40∞C to +85∞C 28-Lead TSSOP 67.7∞C/W1 RU-28 AD8325ARUZ-REEL2 –40∞C to +85∞C 28-Lead TSSOP 67.7∞C/W1 RU-28 AD8325-EVAL Evaluation Board 1Thermal Resistance measured on SEMI standard 4-layer board. 2Z = Pb-free part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection. Although the AD8325 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description
1 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. 2 SDATA Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the MSB (Most Significant Bit) first. 3 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master- slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. This requires the input serial data word to be valid at or before this clock transition. 4, 8, 11, 12, GND Common External Ground Reference. 13, 16, 17, 18, 22, 24, 28 5, 9, 10, 19, VCC Common Positive External Supply Voltage. A 0.1 mF capacitor must decouple each pin. 20, 23, 27 6 TXEN Logic “0” disables transmission. Logic “1” enables transmission. 7 SLEEP Low Power Sleep Mode. Logic 0 enables Sleep mode, where ZOUT goes to 400 W and supply current is reduced to 4 mA. Logic 1 enables normal operation. 14 OUT– Negative Output Signal. 15 OUT+ Positive Output Signal. 21 BYP Internal Bypass. This pin must be externally ac-coupled (0.1 mF cap). 25 VIN+ Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 mF capacitor. 26 VIN– Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 mF capacitor. –4– REV. A Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS LOGIC INPUTS TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics APPLICATIONS General Application Operational Description SPI Programming and Gain Adjustment Input Bias, Impedance, and Termination Output Bias, Impedance, and Termination Power Supply Decoupling, Grounding, and Layout Considerations Initial Power-Up Between Burst Operation Distortion, Adjacent Channel Power, and DOCSIS Noise and DOCSIS Evaluation Board Features and Operation Overshoot on PC Printer Ports Transformer and Diplexer Differential Inputs Single-Ended-to-Differential Input Differential Input Installing the Visual Basic Control Software Running the Software Controlling the Gain/Attenuation of the AD8325 Transmit Enable, Transmit Disable, and Sleep Memory Section EVALUATION BOARD FEATURES AND OPERATION EVALUATION BOARD BILL OF MATERIALS OUTLINE DIMENSIONS Revision History
Supply Voltage +VS Pins 5, 9, 10, 19, 20, 23, 27 . 6 V
DATEN 1 28 GND
Input Voltages
SDATA 2 27 VCC
Pins 25, 26 . ± 0.5 V
CLK 3 26 VIN–
Pins 1, 2, 3, 6, 7 . –0.8 V to +5.5 V
GND 4 25 VIN+
Internal Power Dissipation
V 5 24 GND CC
TSSOP . 0.9 W
TXEN 6 23 V AD8325 CC
Operating Temperature Range . –40∞C to +85∞C
SLEEP 7 TOP VIEW 22 GND
Storage Temperature Range . –65∞C to +150∞C
(Not to Scale) GND 8 21 BYP
Lead Temperature, Soldering 60 seconds . 300∞C
V 9 20 CC VCC
*Stresses above those listed under Absolute Maximum Ratings may cause perma
V 10 19 CC VCC
nent damage to the device. This is a stress rating only; functional operation of the
GND 11 18 GND
device at these or any other conditions above those indicated in the operational
GND 12 17 GND
section of this specification is not implied. Exposure to absolute maximum rating
GND 13 16 GND
conditions for extended periods may affect device reliability.
OUT– 14 15 OUT+ ORDERING GUIDE Model Temperature Range Package Description
�
JA Package Option
AD8325ARU –40∞C to +85∞C 28-Lead TSSOP 67.7∞C/W1 RU-28 AD8325ARU-REEL –40∞C to +85∞C 28-Lead TSSOP 67.7∞C/W1 RU-28 AD8325ARUZ2 –40∞C to +85∞C 28-Lead TSSOP 67.7∞C/W1 RU-28 AD8325ARUZ-REEL2 –40∞C to +85∞C 28-Lead TSSOP 67.7∞C/W1 RU-28 AD8325-EVAL Evaluation Board 1Thermal Resistance measured on SEMI standard 4-layer board. 2Z = Pb-free part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection. Although the AD8325 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description
1 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. 2 SDATA Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the MSB (Most Significant Bit) first. 3 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master- slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. This requires the input serial data word to be valid at or before this clock transition. 4, 8, 11, 12, GND Common External Ground Reference. 13, 16, 17, 18, 22, 24, 28 5, 9, 10, 19, VCC Common Positive External Supply Voltage. A 0.1 mF capacitor must decouple each pin. 20, 23, 27 6 TXEN Logic “0” disables transmission. Logic “1” enables transmission. 7 SLEEP Low Power Sleep Mode. Logic 0 enables Sleep mode, where ZOUT goes to 400 W and supply current is reduced to 4 mA. Logic 1 enables normal operation. 14 OUT– Negative Output Signal. 15 OUT+ Positive Output Signal. 21 BYP Internal Bypass. This pin must be externally ac-coupled (0.1 mF cap). 25 VIN+ Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 mF capacitor. 26 VIN– Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 mF capacitor. –4– REV. A Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS LOGIC INPUTS TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics APPLICATIONS General Application Operational Description SPI Programming and Gain Adjustment Input Bias, Impedance, and Termination Output Bias, Impedance, and Termination Power Supply Decoupling, Grounding, and Layout Considerations Initial Power-Up Between Burst Operation Distortion, Adjacent Channel Power, and DOCSIS Noise and DOCSIS Evaluation Board Features and Operation Overshoot on PC Printer Ports Transformer and Diplexer Differential Inputs Single-Ended-to-Differential Input Differential Input Installing the Visual Basic Control Software Running the Software Controlling the Gain/Attenuation of the AD8325 Transmit Enable, Transmit Disable, and Sleep Memory Section EVALUATION BOARD FEATURES AND OPERATION EVALUATION BOARD BILL OF MATERIALS OUTLINE DIMENSIONS Revision History
