Datasheet AD8325 (Analog Devices) - 7

AD8325 APPLICATIONS
with a transformer, the stated gain values already take into account
General Application
the losses associated with the transformer. The AD8325 is primarily intended for use as the upstream The gain transfer function is as follows: power amplifier (PA) in DOCSIS (Data Over Cable Service AV = 30.0 dB – (0.7526 dB Interface Specifications) certified cable modems and CATV ¥ (79 – CODE)) for 0 £ CODE £ 79 set-top boxes. Upstream data is modulated in QPSK or QAM where AV is the gain in dB and CODE is the decimal equivalent format, and done with DSP or a dedicated QPSK/QAM modula­ of the 8-bit word. tor. The amplifier receives its input signal from the QPSK/QAM Valid gain codes are from 0 to 79. Figure 4 shows the gain char­ modulator or from a DAC. In either case the signal must be acteristics of the AD8325 for all possible values in an 8-bit low-pass filtered before being applied to the amplifier. Because word. Note that maximum gain is achieved at Code 79. From the distance from the cable modem to the central office will vary Code 80 through 127, the 5.25 dB of attenuation from the ver­ with each subscriber, the AD8325 must be capable of varying its nier stage is being applied over every eight codes, resulting in output power by applying gain or attenuation to ensure that all the sawtooth characteristic at the top of the gain range. Because signals arriving at the central office are of the same amplitude. the eighth bit is a “don’t care” bit, the characteristic for codes 0 The upstream signal path contains components such as a trans­ through 127 repeats from Codes 128 through 255. former and diplexer that will result in some amount of power loss. Therefore, the amplifier must be capable of providing enough
30
power into a 75 W load to overcome these losses without sacri­
25
ficing the integrity of the output signal.
20 Operational Description 15
The AD8325 is composed of four analog functions in the power-
10
up or forward mode. The input amplifier (preamp) can be used
5
single-endedly or differentially. If the input is used in the differ­ ential configuration, it is imperative that the input signals are 180
0
degrees out of phase and of equal amplitudes. This will ensure
GAIN – dB –5
proper gain accuracy and harmonic performance. The preamp
–10
stage drives a vernier stage that provides the fine tune gain
–15
adjustment. The 0.7526 dB step resolution is implemented in
–20
the vernier stage and provides a total of approximately 5.25 dB of
–25
attenuation. After the vernier stage, a DAC provides the bulk
–30
of the AD8325’s attenuation (9 bits or 54 dB). The signals in the
0 32 64 96 128 160 192 224 256 GAIN CODE – Decimal
preamp and vernier gain blocks are differential to improve the PSRR and linearity. A differential current is fed from the DAC Figure 4. Gain vs. Gain Code into the output stage, which amplifies these currents to the
Input Bias, Impedance, and Termination
appropriate levels necessary to drive a 75 W load. The output The VIN+ and VIN– inputs have a dc bias level of approximately stage utilizes negative feedback to implement a differential VCC/2, therefore the input signal should be ac-coupled. The 75 W output impedance. This eliminates the need for external differential input impedance is approximately 1600 W while the matching resistors needed in typical video (or video filter) ter­ single-ended input impedance is 800 W. If the AD8325 is being mination requirements. operated in a single-ended input configuration with a desired
SPI Programming and Gain Adjustment
input impedance of 75 W, the VIN+ and VIN– inputs should be Gain programming of the AD8325 is accomplished using a terminated as shown in Figure 5. If an input impedance other serial peripheral interface (SPI) and three digital control lines, than 75 W is desired, the values of R1 and R2 in Figure 5 can be DATEN, SDATA, and CLK. To change the gain, eight bits calculated using the following equations: of data are streamed into the serial shift register through the Z = IN R 1 800 SDATA port. The SDATA load sequence begins with a falling edge on the DATEN pin, thus activating the CLK line. With the R2 = Z IN R1 CLK line activated, data on the SDATA line is clocked into the serial shift register Most Significant Bit (MSB) first, on the rising
ZIN = 75
� edge of each CLK pulse. Because only a 7-bit shift register is
–
used, the MSB of the 8-bit word is a “don’t care” bit and is shifted
R1 = 82.5
�
AD8325
out of the register on the eighth clock pulse. A rising edge on
+
the DATEN line latches the contents of the shift register into
R2 = 39.2
� the attenuator core resulting in a well controlled change in the output signal level. The serial interface timing for the AD8325 is Figure 5. Single-Ended Input Termination shown in Figures 2 and 3. The programmable gain range of the AD8325 is –29.45 dB to +30 dB and scales 0.7526 dB per least significant bit (LSB). Because the AD8325 was characterized REV. A –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS LOGIC INPUTS TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics APPLICATIONS General Application Operational Description SPI Programming and Gain Adjustment Input Bias, Impedance, and Termination Output Bias, Impedance, and Termination Power Supply Decoupling, Grounding, and Layout Considerations Initial Power-Up Between Burst Operation Distortion, Adjacent Channel Power, and DOCSIS Noise and DOCSIS Evaluation Board Features and Operation Overshoot on PC Printer Ports Transformer and Diplexer Differential Inputs Single-Ended-to-Differential Input Differential Input Installing the Visual Basic Control Software Running the Software Controlling the Gain/Attenuation of the AD8325 Transmit Enable, Transmit Disable, and Sleep Memory Section EVALUATION BOARD FEATURES AND OPERATION EVALUATION BOARD BILL OF MATERIALS OUTLINE DIMENSIONS Revision History