Datasheet ADSP-BF700, 701, 702, 703, 704, 705, 706, 707 (Analog Devices) - 7

link to page 7
ADSP-BF700/701/702/703/704/705/706/707
output enable and the input enable of a GPIO pin are both active, the data signal before the pad driver is looped back to the receive path for the same GPIO pin.
PROCESSOR MEMORY MAP 0x FFFF FFFF - MEMORY ARCHITECTURE
The processor views memory as a single unified 4G byte address
Reserved
space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory
0x 9000 0000 -
portions of this address space are arranged in a hierarchical
DDR2 or LPDDR Memory (256 MB)
structure to provide a good cost/performance balance of some
0x 8000 0000 - Y
very fast, low-latency core-accessible memory as cache or
Reserved
SRAM, and larger, lower-cost and performance interface-acces-
0x 7400 2000 - MEMOR
sible memory systems. See Figure 3.
EXTERNAL Static Memory Block 1 (8 KB) y 0x 7400 0000 - Reserved Internal (Core-Accessible) Memory 0x 7000 2000 - Static Memor Static Memory Block 0 (8 KB) 0x 7000 0000 -
The L1 memory system is the highest-performance memory available to the Blackfin+ processor core.
Reserved
The core has its own private L1 memory. The modified Harvard
0x 4800 0000 -
architecture supports two concurrent 32-bit data accesses along
SPI2 Memory (128 MB)
with an instruction fetch at full processor speed which provides
0x 4000 0000 -
high-bandwidth processor performance. In the core, a 64K byte
Reserved 0x 3800 0500 -
block of data memory partners with an 64K byte memory block
OTP Memory (1 KB)
for instruction storage. Each data block is multibanked for effi-
0x 3800 0000 -
cient data exchange through DMA and can be configured as
Reserved
SRAM. Alternatively, 16K bytes of each block can be configured
0x 2030 1000 -
in L1 cache mode. The four-way set-associative instruction
STM Memory (4 KB) 0x 2030 0000 -
cache and the 2 two-way set-associative data caches greatly
System MMR Registers (3 MB) 0x 2000 0000 -
accelerate memory access performance, especially when access-
Core MMR Registers (4 MB)
ing external memories.
0x 1FC0 0000 - Reserved
The L1 memory domain also features a 8K byte data SRAM
0x 11B0 2000 -
block which is ideal for storing local variables and the software
L1 Data Block C (8 KB) 0x 11B0 0000 -
stack. All L1 memory is protected by a multi-parity-bit concept,
Reserved 0x 11A1 0000 -
regardless of whether the memory is operating in SRAM or
L1 Instruction SRAM/Cache (16 KB) 0x 11A0 C000 -
cache mode.
L1 Y L1 Instruction SRAM (48 KB) 0x 11A0 0000 - Instruction
Outside of the L1 domain, L2 and L3 memories are arranged
Reserved 0x 1190 8000 - INTERNAL MEMOR
using a Von Neumann topology. The L2 memory domain is a
L1 Data Block B SRAM/Cache (16 KB) k B
unified instruction and data memory and can hold any mixture
0x 1190 4000 - L1 Data Block B SRAM (16 KB) L1 Data Bloc
of code and data required by the system design. The L2 memory
0x 1190 0000 - Reserved
domain is accessible by the Blackfin+ core through a dedicated
0x 1180 8000 - L1 Data Block A SRAM/Cache (16 KB)
64-bit interface. It operates at SYSCLK frequency.
k A 0x 1180 4000 - L1 Data Block A SRAM (16 KB) L1 Data Bloc
The processor features up to 1M byte of L2 SRAM, which is
0x 1180 0000 -
ECC-protected and organized in eight banks. Individual banks
Reserved 0x 0810 0000 -
can be made private to any system master. There is also a
L2 SRAM (1024 KB) 0x 0800 0000 -
512K byte single-bank ROM in the L2 domain. It contains boot
Reserved
code, security code, and general-purpose ROM space.
0x 0408 0000 - L2 ROM (448 KB) 0x 0401 0000 - OTP Memory Boot ROM (64 KB) 0x 0400 0000 -
The processor features 1 kB of one-time-programmable (OTP)
Reserved 0x 0000 0000 -
memory, which is memory-map accessible. This memory stores a unique chip identification and is used to support secure-boot Figure 3. ADSP-BF706/ADSP-BF707 Internal/External Memory Map and secure operation. Rev. D | Page 7 of 114 | February 2019 Document Outline Blackfin+ Core Embedded Processor Features Peripherals Features Memory Table of Contents Revision History General Description Blackfin+ Processor Core Instruction Set Description Processor Infrastructure DMA Controllers Event Handling Trigger Routing Unit (TRU) General-Purpose I/O (GPIO) Pin Interrupts Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory OTP Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Security Features Security Features Disclaimer Processor Safety Features Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers Serial Ports (SPORTs) General-Purpose Counters Parallel Peripheral Interface (PPI) Serial Peripheral Interface (SPI) Ports SPI Host Port (SPIHP) UART Ports 2-Wire Controller Interface (TWI) Mobile Storage Interface (MSI) Controller Area Network (CAN) USB 2.0 On-the-Go Dual-Role Device Controller Housekeeping ADC (HADC) System Crossbars (SCB) Power and Clock Management System Crystal Oscillator and USB Crystal Oscillator Real-Time Clock Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit Debug Access Port Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits ADSP-BF706 EZ-KIT Mini Blackfin Low Power Imaging Platform (BLIP) Software Add-Ins for CrossCore Embedded Studio Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF70x Detailed Signal Descriptions 184-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 184-Ball CSP_BGA 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions GPIO Multiplexing for 12 mm × 12 mm 88-Lead LFCSP (QFN) ADSP-BF70x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing General-Purpose I/O Port Timing (GPIO) Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Debug Interface (JTAG Emulation Port) Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing Enhanced Parallel Peripheral Interface Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) Mobile Storage Interface (MSI) Controller Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Numerical by Ball Number) ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignments (Numerical by Lead Number) Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide