Datasheet ADSP-BF700, 701, 702, 703, 704, 705, 706, 707 (Analog Devices) - 8

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ADSP-BF700/701/702/703/704/705/706/707 Static Memory Controller (SMC)
The following hardware-accelerated cryptographic ciphers are supported: The SMC can be programmed to control up to two blocks of external memories or memory-mapped devices, with very flexi- • AES in ECB, CBC, ICM, and CTR modes with 128-, 192-, ble timing parameters. Each block occupies a 8K byte segment and 256-bit keys regardless of the size of the device used. • DES in ECB and CBC mode with 56-bit key
Dynamic Memory Controller (DMC)
• 3DES in ECB and CBC mode with 3x 56-bit key The DMC includes a controller that supports JESD79-2E com- The following hardware-accelerated hash functions are patible double-data-rate (DDR2) SDRAM and JESD209A low- supported: power DDR (LPDDR) SDRAM devices. The DMC PHY fea- • SHA-1 tures on-die termination on all data and data strobe pins that can be used during reads. • SHA-2 with 224-bit and 256-bit digest • HMAC transforms for SHA-1 and SHA-2
I/O Memory Space
Public key accelerator is available to offload computation-inten- The processor does not define a separate I/O space. All sive public key cryptography operations. resources are mapped through the flat 32-bit address space. On- chip I/O devices have their control registers mapped into mem- Both a hardware-based nondeterministic random number gen- ory-mapped registers (MMRs) at addresses in a region of the erator and pseudo-random number generator are available. The 4G byte address space. These are separated into two smaller TRNG also provides HW post-processing to meet NIST blocks, one which contains the control MMRs for all core func- requirements of FIPS 140-2, while the PRNG is ANSI X9.31 tions, and the other which contains the registers needed for compliant. setup and control of the on-chip peripherals outside of the core. Secure boot is also available with 224-bit elliptic curve digital The MMRs are accessible only in supervisor mode and appear signatures ensuring integrity and authenticity of the boot as reserved space to on-chip peripherals. stream. Optionally, confidentiality is also ensured through AES- 128 encryption.
Booting
The processor has several mechanisms for automatically loading
CAUTION
internal and external memory after a reset. The boot mode is This product includes security features that can be defined by the SYS_BMODE input pins dedicated for this pur- used to protect embedded nonvolatile memory pose. There are two categories of boot modes. In master boot contents and prevent execution of unauthorized mode, the processor actively loads data from serial memories. In code. When security is enabled on this device (either by the ordering party or the subsequent slave boot modes, the processor receives data from external host receiving parties), the ability of Analog Devices to devices. conduct failure analysis on returned devices is limited. Contact Analog Devices for details on the The boot modes are shown in Table 2. These modes are imple- failure analysis limitations for this device. mented by the SYS_BMODE bits of the reset configuration register and are sampled during power-on resets and software- initiated resets. Secure debug is also employed to allow only trusted users to access the system with debug tools.
Table 2. Boot Modes SECURITY FEATURES DISCLAIMER SYS_BMODE Setting Boot Mode
To our knowledge, the Security Features, when used in accor- 00 No Boot/Idle dance with the data sheet and hardware reference manual 01 SPI2 Master specifications, provide a secure method of implementing code and data safeguards. However, Analog Devices does not guaran- 10 SPI2 Slave tee that this technology provides absolute security. 11 UART0 Slave ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES
SECURITY FEATURES
THAT THE SECURITY FEATURES CANNOT BE The ADSP-BF70x processor supports standards-based hard- BREACHED, COMPROMISED, OR OTHERWISE CIRCUM- ware-accelerated encryption, decryption, authentication, and VENTED AND IN NO EVENT SHALL ANALOG DEVICES true random number generation. BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF DATA, INFORMATION, PHYSICAL PROP- ERTY, OR INTELLECTUAL PROPERTY. Rev. D | Page 8 of 114 | February 2019 Document Outline Blackfin+ Core Embedded Processor Features Peripherals Features Memory Table of Contents Revision History General Description Blackfin+ Processor Core Instruction Set Description Processor Infrastructure DMA Controllers Event Handling Trigger Routing Unit (TRU) General-Purpose I/O (GPIO) Pin Interrupts Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory OTP Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Security Features Security Features Disclaimer Processor Safety Features Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers Serial Ports (SPORTs) General-Purpose Counters Parallel Peripheral Interface (PPI) Serial Peripheral Interface (SPI) Ports SPI Host Port (SPIHP) UART Ports 2-Wire Controller Interface (TWI) Mobile Storage Interface (MSI) Controller Area Network (CAN) USB 2.0 On-the-Go Dual-Role Device Controller Housekeeping ADC (HADC) System Crossbars (SCB) Power and Clock Management System Crystal Oscillator and USB Crystal Oscillator Real-Time Clock Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit Debug Access Port Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits ADSP-BF706 EZ-KIT Mini Blackfin Low Power Imaging Platform (BLIP) Software Add-Ins for CrossCore Embedded Studio Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF70x Detailed Signal Descriptions 184-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 184-Ball CSP_BGA 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions GPIO Multiplexing for 12 mm × 12 mm 88-Lead LFCSP (QFN) ADSP-BF70x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing General-Purpose I/O Port Timing (GPIO) Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Debug Interface (JTAG Emulation Port) Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing Enhanced Parallel Peripheral Interface Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) Mobile Storage Interface (MSI) Controller Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Numerical by Ball Number) ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignments (Numerical by Lead Number) Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide