Datasheet ADSP-BF504 (Analog Devices) - 7

ADSP-BF504 Table 3. System Interrupt Controller (SIC) General-Purpose Peripheral Default Core Peripheral Interrupt Source Interrupt (at Reset) Interrupt ID Interrupt ID SIC Registers
PLL Wakeup Interrupt IVG7 0 0 IAR0 IMASK0, ISR0, IWR0 DMA Error (generic) IVG7 1 0 IAR0 IMASK0, ISR0, IWR0 PPI Status IVG7 2 0 IAR0 IMASK0, ISR0, IWR0 SPORT0 Status IVG7 3 0 IAR0 IMASK0, ISR0, IWR0 SPORT1 Status IVG7 4 0 IAR0 IMASK0, ISR0, IWR0 UART0 Status IVG7 5 0 IAR0 IMASK0, ISR0, IWR0 UART1 Status IVG7 6 0 IAR0 IMASK0, ISR0, IWR0 SPI0 Status IVG7 7 0 IAR0 IMASK0, ISR0, IWR0 SPI1 Status IVG7 8 0 IAR1 IMASK0, ISR0, IWR0 CAN Status IVG7 9 0 IAR1 IMASK0, ISR0, IWR0 RSI Mask 0 Interrupt IVG7 10 0 IAR1 IMASK0, ISR0, IWR0 Reserved — 11 — IAR1 IMASK0, ISR0, IWR0 CNT0 Interrupt IVG8 12 1 IAR1 IMASK0, ISR0, IWR0 CNT1 Interrupt IVG8 13 1 IAR1 IMASK0, ISR0, IWR0 DMA Channel 0 (PPI Rx/Tx) IVG9 14 2 IAR1 IMASK0, ISR0, IWR0 DMA Channel 1 (RSI Rx/Tx) IVG9 15 2 IAR1 IMASK0, ISR0, IWR0 DMA Channel 2 (SPORT0 Rx) IVG9 16 2 IAR2 IMASK0, ISR0, IWR0 DMA Channel 3 (SPORT0 Tx) IVG9 17 2 IAR2 IMASK0, ISR0, IWR0 DMA Channel 4 (SPORT1 Rx) IVG9 18 2 IAR2 IMASK0, ISR0, IWR0 DMA Channel 5 (SPORT1 Tx) IVG9 19 2 IAR2 IMASK0, ISR0, IWR0 DMA Channel 6 (SPI0 Rx/Tx) IVG10 20 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 7 (SPI1 Rx/Tx) IVG10 21 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 8 (UART0 Rx) IVG10 22 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 9 (UART0 Tx) IVG10 23 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 10 (UART1 Rx) IVG10 24 3 IAR3 IMASK0, ISR0, IWR0 DMA Channel 11 (UART1 Tx) IVG10 25 3 IAR3 IMASK0, ISR0, IWR0 CAN Receive IVG11 26 4 IAR3 IMASK0, ISR0, IWR0 CAN Transmit IVG11 27 4 IAR3 IMASK0, ISR0, IWR0 TWI IVG11 28 4 IAR3 IMASK0, ISR0, IWR0 Port F Interrupt A IVG11 29 4 IAR3 IMASK0, ISR0, IWR0 Port F Interrupt B IVG11 30 4 IAR3 IMASK0, ISR0, IWR0 Reserved — 31 — IAR3 IMASK0, ISR0, IWR0 Timer 0 IVG12 32 5 IAR4 IMASK1, ISR1, IWR1 Timer 1 IVG12 33 5 IAR4 IMASK1, ISR1, IWR1 Timer 2 IVG12 34 5 IAR4 IMASK1, ISR1, IWR1 Timer 3 IVG12 35 5 IAR4 IMASK1, ISR1, IWR1 Timer 4 IVG12 36 5 IAR4 IMASK1, ISR1, IWR1 Timer 5 IVG12 37 5 IAR4 IMASK1, ISR1, IWR1 Timer 6 IVG12 38 5 IAR4 IMASK1, ISR1, IWR1 Timer 7 IVG12 39 5 IAR4 IMASK1, ISR1, IWR1 Port G Interrupt A IVG12 40 5 IAR5 IMASK1, ISR1, IWR1 Port G Interrupt B IVG12 41 5 IAR5 IMASK1, ISR1, IWR1 MDMA Stream 0 IVG13 42 6 IAR5 IMASK1, ISR1, IWR1 Rev. C | Page 7 of 51 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low-Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory External (Interface-Accessible) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Up/Down Counters and Thumbwheel Interfaces 3-Phase PWM Units Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions RSI Interface Controller Area Network (CAN) Interface TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF504 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) ACM Interface Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF504 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Processor—Absolute Maximum Ratings ESD Sensitivity Processor—Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing JTAG Test And Emulation Port Timing Processor—Output Drive Currents Processor—Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Processor—Environmental Conditions 88-Lead LFCSP Lead Assignment Outline Dimensions Ordering Guide