Datasheet ADSP-BF512, BF514, BF516, BF518 (Analog Devices)

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Blackfin Embedded Processor ADSP-BF512 /BF514 /BF516 /BF518 FEATURES PERIPHERALS Up to 400 MHz high performance Blackfin processor IEEE 802.3-compliant 10/100 Ethernet MAC with IEEE 1588 Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, support (ADSP-BF518 only) 40-bit shifter Parallel peripheral interface (PPI), supporting ITU-R 656 RISC-like register and instruction model for ease of video data formats programming and compiler-friendly support 2 dual-channel, full-duplex synchronous serial ports Advanced debug, trace, and performance monitoring (SPORTs), supporting 8 stereo I2S channels Wide range of operating voltages. See Operating Conditions 12 peripheral DMAs, 2 mastered by the Ethernet MAC Qualified for Automotive Applications. See Automotive 2 memory-to-memory DMAs with external request lines Products Event handler with 56 interrupt inputs 168-ball CSP_BGA or 176-lead LQFP_EP (with exposed pad) 2 serial peripheral interfaces (SPI) MEMORY Removable storage interface (RSI) controller for MMC, SD, SDIO, and CE-ATA 116K bytes of on-chip memory 2 UARTs with IrDA support External memory controller with glueless support for SDRAM 2-wire interface (TWI) controller and asynchronous 8-bit and 16-bit memories Eight 32-bit timers/counters with PWM support Flexible booting options from OTP memory, external 3-phase 16-bit center-based PWM unit SPI/parallel memories, or from SPI/UART host devices 32-bit general-purpose counter Code security with Lockbox secure technology Real-time clock (RTC) and watchdog timer One-time-programmable (OTP) memory 32-bit core timer Memory management unit providing memory protection 40 general-purpose I/Os (GPIOs) Debug/JTAG interface On-chip PLL capable of frequency multiplication RTC OTP WATCHDOG TIMER PERIPHERAL ACCESS BUS COUNTER JTAG TEST AND EMULATION 3-PHASE PWM TIMER7–0 TWI INTERRUPT
B
CONTROLLER SPORT1-0 RSI (SDIO) PORTS L1 L1 DMA INSTRUCTION DATA PPI CONTROLLER MEMORY MEMORY UART1–0 DMA EXTERNAL 16 EMAC DMA CORE BUS BUS EXTERNAL ACCESS BUS SPI1 BOOT EXTERNAL PORT FLASH, SPI0 ROM SDRAM CONTROL
Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
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Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time Programmable Memory I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Real-Time Clock Watchdog Timer Timers 3-Phase PWM General-Purpose (GP) Counter Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports 2-Wire Interface (TWI) Removable Storage Interface (RSI) 10/100 Ethernet MAC IEEE 1588 Support Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) Code Security with Lockbox Secure Technology Lockbox Secure Technology Disclaimer Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Interface Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 176-Lead LQFP_EP Lead Assignment 168-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide