Datasheet ADSP-BF512, BF514, BF516, BF518 (Analog Devices) - 5

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ADSP-BF512 /BF514 /BF516 /BF518
The Blackfin processor assembly language uses an algebraic syn- The on-chip L1 memory system is the highest-performance tax for ease of coding and readability. The architecture has been memory available to the Blackfin processor. The off-chip mem- optimized for use in conjunction with the C/C++ compiler, ory system, accessed through the external bus interface unit resulting in fast and efficient software implementations. (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of
MEMORY ARCHITECTURE
physical memory. The ADSP-BF51x processors view memory as a single unified The memory DMA controller provides high bandwidth data- 4G byte address space, using 32-bit addresses. All resources, movement capability. It can perform block transfers of code or including internal memory, external memory, and I/O control data between the internal memory and the external registers, occupy separate sections of this common address memory spaces. space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance
Internal (On-Chip) Memory
balance of some very fast, low-latency on-chip memory as cache The ADSP-BF51x processors have three blocks of on-chip or SRAM, and larger, lower-cost and performance off-chip memory that provide high bandwidth access to the core. memory systems. The memory map for both internal and exter- nal memory space is shown in Figure 3. The first block is the L1 instruction memory, consisting of 48K bytes SRAM, of which 16K bytes can be configured as a four-way set-associative cache. This memory is accessed at full processor speed.
0xFFFF FFFF CORE MMR REGISTERS (2M BYTES) 0xFFE0 0000
The second on-chip memory block is the L1 data memory, con-
SYSTEM MMR REGISTERS (2M BYTES)
sisting of up to two banks of up to 32K bytes each. Each memory
0xFFC0 0000 RESERVED
bank is configurable, offering both cache and SRAM functional-
0xFFB0 1000
ity. This memory block is accessed at full processor speed.
SCRATCHPAD SRAM (4K BYTES) 0xFFB0 0000
The third memory block is a 4K byte scratchpad SRAM which
RESERVED 0xFFA1 4000
runs at the same speed as the L1 memories, but is only accessible
INSTRUCTION BANK C SRAM/CACHE (16K BYTES) 0xFFA1 0000 P
as data SRAM and cannot be configured as cache memory.
A RESERVED M 0xFFA0 8000 Y External (Off-Chip) Memory INSTRUCTION BANK B SRAM (16K BYTES) R 0xFFA0 4000 MO E INSTRUCTION BANK A SRAM (16K BYTES)
External memory is accessed via the EBIU. This 16-bit interface
M 0xFFA0 0000 L
provides a glueless connection to a bank of synchronous DRAM
RESERVED A N 0xFF90 8000
(SDRAM) as well as up to four banks of asynchronous memory
DATA BANK B SRAM / CACHE (16K BYTES) ER T
devices including flash, EPROM, ROM, SRAM, and memory
0xFF90 4000 IN DATA BANK B SRAM (16K BYTES)
mapped I/O devices.
0xFF90 0000 RESERVED
The SDRAM controller can be programmed to interface to up
0xFF80 8000 DATA BANK A SRAM / CACHE (16K BYTES)
to 128M bytes of SDRAM. A separate row can be open for each
0xFF80 4000
SDRAM internal bank, and the SDRAM controller supports up
DATA BANK A SRAM (16K BYTES) 0xFF80 0000
to four internal SDRAM banks, improving overall performance.
RESERVED 0xEF00 8000
The asynchronous memory controller can be programmed to
BOOT ROM (32K BYTES) 0xEF00 0000
control up to four banks of devices with very flexible timing
P RESERVED A
parameters for a wide variety of devices. Each bank occupies a
0x2040 0000 M ASYNC MEMORY BANK 3 (1M BYTES) Y
1M byte segment regardless of the size of the devices used, so
R 0x2030 0000 O
that these banks are only contiguous if each is fully populated
ASYNC MEMORY BANK 2 (1M BYTES) M E 0x2020 0000 M
with 1M byte of memory.
ASYNC MEMORY BANK 1 (1M BYTES) L 0x2010 0000 NA R One-Time Programmable Memory ASYNC MEMORY BANK 0 (1M BYTES) E 0x2000 0000 T X RESERVED E
The processors have 64K bits of one-time programmable non-
0x08 00 0000
volatile memory that can be programmed by the developer only
SDRAM MEMORY (16M BYTES - 128M BYTES) 0x0000 0000
once. It includes the array and logic to support read access and programming. Additionally, its pages can be write protected. Figure 3. ADSP-BF51x Internal/External Memory Map The OTP memory allows both public and private data to be stored on-chip. In addition to storing public and private key data for applications requiring security, OTP allows developers to store completely user-definable data such as customer ID, product ID, and MAC address. Therefore, generic parts can be supplied which are then programmed and protected by the developer within this non-volatile memory. Rev. E | Page 5 of 63 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time Programmable Memory I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Real-Time Clock Watchdog Timer Timers 3-Phase PWM General-Purpose (GP) Counter Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports 2-Wire Interface (TWI) Removable Storage Interface (RSI) 10/100 Ethernet MAC IEEE 1588 Support Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) Code Security with Lockbox Secure Technology Lockbox Secure Technology Disclaimer Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Interface Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 176-Lead LQFP_EP Lead Assignment 168-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide