Datasheet ADSP-BF512, BF514, BF516, BF518 (Analog Devices) - 9

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ADSP-BF512 /BF514 /BF516 /BF518
The SPI port baud rate and clock phase/polarities are program- • A ten-signal external interface with clock, command, and mable, and it has an integrated DMA channel, configurable to up to eight data lines support transmit or receive data streams. The DMA channel of • Card detection using one of the data signals the SPI can only service unidirectional accesses at any given time. • Card interface clock generation from SCLK • SDIO interrupt and read wait features
UART Ports
• CE-ATA command completion signal recognition and The processors provide two full-duplex universal asynchronous disable receiver/transmitter (UART) ports, which are fully compatible with PC-standard UARTs. Each UART port provides a
10/100 Ethernet MAC
simplified UART interface to other peripherals or hosts, sup- The ADSP-BF516 and ADSP-BF518 processors offer the capa- porting full-duplex, DMA-supported, asynchronous transfers of bility to directly connect to a network by way of an embedded serial data. A UART port includes support for five to eight data fast Ethernet media access controller (MAC) that supports both bits, and none, even, or odd parity. Optionally, an additional 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec) opera- address bit can be transferred to interrupt only addressed nodes tion. The 10/100 Ethernet MAC peripheral on the processor is in multi-drop bus (MDB) systems. A frame is terminates by one, fully compliant to the IEEE 802.3-2002 standard and it provides one and a half, two or two and a half stop bits. programmable features designed to minimize supervision, bus The UART ports support automatic hardware flow control use, or message processing by the rest of the processor system. through the Clear To Send (CTS) input and Request To Send Some standard features are: (RTS) output with programmable assertion FIFO levels. • Support of MII and RMII protocols for external PHYs To help support the Local Interconnect Network (LIN) proto- cols, a special command causes the transmitter to queue a break • Full duplex and half duplex modes command of programmable bit length into the transmit buffer. • Data framing and encapsulation: generation and detection Similarly, the number of stop bits can be extended by a pro- of preamble, length padding, and FCS grammable inter-frame space. • Media access management (in half-duplex operation): col- The capabilities of the UARTs are further extended with sup- lision and contention handling, including control of port for the Infrared Data Association (IrDA®) serial infrared retransmission of collision frames and of back-off timing physical layer link specification (SIR) protocol. • Flow control (in full-duplex operation): generation and
2-Wire Interface (TWI)
detection of pause frames The processors include a TWI module for providing a simple • Station management: generation of MDC/MDIO frames exchange method of control data between multiple devices. The for read-write access to PHY registers TWI is compatible with the widely used I2C® bus standard. The • Operating range for active and sleep operating modes, see TWI module offers the capabilities of simultaneous master and Table 39 and Table 40 slave operation, support for both 7-bit addressing and multime- • Internal loopback from transmit to receive dia data arbitration. The TWI interface utilizes two signals for transferring clock (SCL) and data (SDA) and supports the pro- Some advanced features are: tocol at speeds up to 400k bits/sec. The TWI interface signals • Buffered crystal output to external PHY for support of a are compatible with 5 V logic levels. single crystal system Additionally, the processor’s TWI module is fully compatible • Automatic checksum computation of IP header and IP with serial camera control bus (SCCB) functionality for easier payload fields of Rx frames control of various CMOS camera sensor devices. • Independent 32-bit descriptor-driven receive and transmit
Removable Storage Interface (RSI)
DMA channels The RSI controller, available on the ADSP-BF514/ADSP- • Frame status delivery to memory through DMA, including BF516/ADSP-BF518 processors, acts as the host interface for frame completion semaphores for efficient buffer queue multi-media cards (MMC), secure digital memory cards (SD management in software Card), secure digital input/output cards (SDIO), and CE-ATA • Tx DMA support for separate descriptors for MAC header hard disk drives. The following list describes the main features and payload to eliminate buffer copy operations of the RSI controller. • Convenient frame alignment modes support even 32-bit • Support for a single MMC, SD memory, SDIO card or CE- alignment of encapsulated receive or transmit IP packet ATA hard disk drive data in memory after the 14-byte MAC header • Support for 1-bit and 4-bit SD modes • Support for 1-bit, 4-bit and 8-bit MMC modes • Support for 4-bit and 8-bit CE-ATA hard disk drives Rev. E | Page 9 of 63 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time Programmable Memory I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Real-Time Clock Watchdog Timer Timers 3-Phase PWM General-Purpose (GP) Counter Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports 2-Wire Interface (TWI) Removable Storage Interface (RSI) 10/100 Ethernet MAC IEEE 1588 Support Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) Code Security with Lockbox Secure Technology Lockbox Secure Technology Disclaimer Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Interface Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 176-Lead LQFP_EP Lead Assignment 168-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide